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Diffstat (limited to 'src/northbridge/intel/ironlake/Kconfig')
| -rw-r--r-- | src/northbridge/intel/ironlake/Kconfig | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig new file mode 100644 index 0000000000..512149bfee --- /dev/null +++ b/src/northbridge/intel/ironlake/Kconfig @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config NORTHBRIDGE_INTEL_IRONLAKE + bool + select CPU_INTEL_MODEL_2065X + select VGA + select INTEL_EDID + select INTEL_GMA_ACPI + select CACHE_MRC_SETTINGS + select HAVE_DEBUG_RAM_SETUP + +if NORTHBRIDGE_INTEL_IRONLAKE + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + # CPU is reset without platform/TPM during romstage + select TPM_STARTUP_IGNORE_POSTINIT + +config MMCONF_BUS_NUMBER + int + default 256 + +config CBFS_SIZE + hex + default 0x100000 + +config VGA_BIOS_ID + string + default "8086,0046" + +config DCACHE_RAM_BASE + hex + default 0xfefc0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +endif |