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path: root/src/northbridge/intel/i945/raminit.c
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Diffstat (limited to 'src/northbridge/intel/i945/raminit.c')
-rw-r--r--src/northbridge/intel/i945/raminit.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 3084072389..53a7455ea9 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2481,6 +2481,9 @@ static void sdram_program_receive_enable(struct sys_info *sysinfo)
{
MCHBAR32(REPC) |= (1 << 0);
+ /* enable upper CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
/* Program Receive Enable Timings */
if (sysinfo->boot_path == BOOT_PATH_RESUME) {
sdram_recover_receive_enable();
@@ -2904,9 +2907,7 @@ void sdram_initialize(int boot_path)
sdram_thermal_management();
/* Normal Operations */
- if (boot_path == BOOT_PATH_NORMAL) {
- sdram_init_complete();
- }
+ sdram_init_complete();
/* Program Receive Enable Timings */
sdram_program_receive_enable(&sysinfo);
@@ -2924,3 +2925,11 @@ void sdram_initialize(int boot_path)
sdram_setup_processor_side();
}
+unsigned long get_top_of_ram(void)
+{
+ /* This will not work if TSEG is in place! */
+ u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+ return (unsigned long) tom;
+}
+