diff options
Diffstat (limited to 'src/northbridge/intel/i945/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/i945/ram_calc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 525a5b9c0e..dbe74c40cf 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -25,6 +25,8 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stdint.h> +#include <stage_cache.h> /* Decodes TSEG region size to bytes. */ u32 decode_tseg_size(const u8 esmramc) @@ -88,6 +90,17 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ |