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Diffstat (limited to 'src/northbridge/intel/i945/ram_calc.c')
-rw-r--r--src/northbridge/intel/i945/ram_calc.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 752c8f901c..525a5b9c0e 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -88,8 +88,6 @@ u32 decode_igd_memory_size(const u32 gms)
return ggc2uma[gms] << 10;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -98,7 +96,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */