aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/i945/northbridge.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel/i945/northbridge.c')
-rw-r--r--src/northbridge/intel/i945/northbridge.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index dde1b110f4..bcecd8854b 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -165,7 +165,6 @@ void northbridge_write_smram(u8 smram)
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,