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path: root/src/northbridge/intel/i945/early_init.c
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Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
-rw-r--r--src/northbridge/intel/i945/early_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 14c66c4e21..f27dca0ac3 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -91,7 +91,7 @@ static void i945m_detect_chipset(void)
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_I945GC
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
#endif
}
@@ -140,7 +140,7 @@ static void i945_detect_chipset(void)
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
#endif
}