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-rw-r--r--src/northbridge/intel/i855pm/Config.lb4
-rw-r--r--src/northbridge/intel/i855pm/northbridge.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/i855pm/Config.lb b/src/northbridge/intel/i855pm/Config.lb
index 72e903b9b1..267986d237 100644
--- a/src/northbridge/intel/i855pm/Config.lb
+++ b/src/northbridge/intel/i855pm/Config.lb
@@ -1,7 +1,7 @@
-uses CONFIG_HAVE_HIGH_TABLES
+uses CONFIG_WRITE_HIGH_TABLES
config chip.h
object northbridge.o
-default CONFIG_HAVE_HIGH_TABLES=1
+default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c
index f6a23914e2..ded93ba753 100644
--- a/src/northbridge/intel/i855pm/northbridge.c
+++ b/src/northbridge/intel/i855pm/northbridge.c
@@ -49,7 +49,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -97,7 +97,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE * 1024;