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-rw-r--r--src/northbridge/intel/i855gme/Config.lb4
-rw-r--r--src/northbridge/intel/i855gme/northbridge.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/i855gme/Config.lb b/src/northbridge/intel/i855gme/Config.lb
index 04634806ab..861a91d3d1 100644
--- a/src/northbridge/intel/i855gme/Config.lb
+++ b/src/northbridge/intel/i855gme/Config.lb
@@ -18,10 +18,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-uses CONFIG_HAVE_HIGH_TABLES
+uses CONFIG_WRITE_HIGH_TABLES
config chip.h
object northbridge.o
-default CONFIG_HAVE_HIGH_TABLES=1
+default CONFIG_WRITE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/i855gme/northbridge.c b/src/northbridge/intel/i855gme/northbridge.c
index 5ad2122d37..932409aead 100644
--- a/src/northbridge/intel/i855gme/northbridge.c
+++ b/src/northbridge/intel/i855gme/northbridge.c
@@ -70,7 +70,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -129,7 +129,7 @@ static void pci_domain_set_resources(device_t dev)
/* ram_resource(dev, idx++, 1024, tolmk - 1024); */
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
high_tables_size = HIGH_TABLES_SIZE * 1024;