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Diffstat (limited to 'src/northbridge/intel/i855')
-rw-r--r--src/northbridge/intel/i855/debug.c40
-rw-r--r--src/northbridge/intel/i855/northbridge.c66
-rw-r--r--src/northbridge/intel/i855/raminit.c34
3 files changed, 70 insertions, 70 deletions
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 05e934dac4..2a9e4076f9 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -104,26 +104,26 @@ static inline void dump_spd_registers(void)
static inline void dump_smbus_registers(void)
{
- int i;
- printk(BIOS_DEBUG, "\n");
- for (i = 1; i < 0x80; i++) {
- unsigned device;
- device = i;
- int j;
- printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
- status = smbus_read_byte(device, j);
- if (status < 0) {
- printk(BIOS_DEBUG, "bad device\n");
- break;
- }
- byte = status & 0xff;
+ int i;
+ printk(BIOS_DEBUG, "\n");
+ for (i = 1; i < 0x80; i++) {
+ unsigned device;
+ device = i;
+ int j;
+ printk(BIOS_DEBUG, "smbus: %02x", device);
+ for (j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ printk(BIOS_DEBUG, "bad device\n");
+ break;
+ }
+ byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index e9b1cac996..bc497a89ef 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -30,33 +30,33 @@
static void northbridge_init(device_t dev)
{
- printk(BIOS_SPEW, "Northbridge init\n");
+ printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x3580,
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x3580,
};
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
+ printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children->sibling;
printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
@@ -107,39 +107,39 @@ static void pci_domain_set_resources(device_t dev)
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_i855_ops = {
- CHIP_NAME("Intel 855 Northbridge")
+ CHIP_NAME("Intel 855 Northbridge")
.enable_dev = enable_dev,
};
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index fe6059d703..43400ab068 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -369,32 +369,32 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
PRINTK_DEBUG(" Sending RAM command 0x%08x\n", reg32);
pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
- // RAM_COMMAND_NORMAL is an exception.
- // It affects only the memory controller and does not need to be "sent" to the DIMMs.
+ // RAM_COMMAND_NORMAL is an exception.
+ // It affects only the memory controller and does not need to be "sent" to the DIMMs.
- if (command != RAM_COMMAND_NORMAL) {
+ if (command != RAM_COMMAND_NORMAL) {
- // Send the command to all DIMMs by accessing a memory location within each
- // NOTE: for mode select commands, some of the location address bits
- // are part of the command
+ // Send the command to all DIMMs by accessing a memory location within each
+ // NOTE: for mode select commands, some of the location address bits
+ // are part of the command
- // Map JEDEC mode bits to i855
- if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
+ // Map JEDEC mode bits to i855
+ if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
/* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));
- }
+ }
- for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
- uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
- if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
+ for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
+ uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
+ if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
- uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
+ uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32((void *)(dimm_start_address + i855_mode_bits));
+ read32((void *)(dimm_start_address + i855_mode_bits));
- // Set the start of the next DIMM
- dimm_start_32M_multiple = dimm_end_32M_multiple;
- }
+ // Set the start of the next DIMM
+ dimm_start_32M_multiple = dimm_end_32M_multiple;
+ }
}
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-09 03:45:15 +0000