diff options
Diffstat (limited to 'src/northbridge/intel/i82830')
| -rw-r--r-- | src/northbridge/intel/i82830/i82830.h | 16 | ||||
| -rw-r--r-- | src/northbridge/intel/i82830/raminit.c | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index 74520b101e..a4b0a86c89 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -21,13 +21,13 @@ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ #define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */ -#define PAM0 0x59 /* Programable Attribute Map #0 (0x00) */ -#define PAM1 0x5a /* Programable Attribute Map #1 (0x00) */ -#define PAM2 0x5b /* Programable Attribute Map #2 (0x00) */ -#define PAM3 0x5c /* Programable Attribute Map #3 (0x00) */ -#define PAM4 0x5d /* Programable Attribute Map #4 (0x00) */ -#define PAM5 0x5e /* Programable Attribute Map #5 (0x00) */ -#define PAM6 0x5f /* Programable Attribute Map #6 (0x00) */ +#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */ +#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */ +#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */ +#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */ +#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */ +#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */ +#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */ #define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */ #define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */ #define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */ @@ -46,7 +46,7 @@ #define ERRCMD 0x94 /* Error Command (0x0000) */ #define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ -#define APSIZE 0xb4 /* Apterture Size (0x00) */ +#define APSIZE 0xb4 /* Aperture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ #endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */ diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c index bd92ac1fe8..7850c8749a 100644 --- a/src/northbridge/intel/i82830/raminit.c +++ b/src/northbridge/intel/i82830/raminit.c @@ -159,7 +159,7 @@ static void initialize_dimm_rows(void) } /*----------------------------------------------------------------------------- -DIMM-independant configuration functions. +DIMM-independent configuration functions. -----------------------------------------------------------------------------*/ struct dimm_size { @@ -206,7 +206,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) } /* SPD byte 31 is the memory size divided by 4 so we - * need to muliply by 4 to get the total size. + * need to multiply by 4 to get the total size. */ sz.side1 *= 4; sz.side2 *= 4; @@ -426,12 +426,12 @@ static void northbridge_set_registers(void) u16 value; int igd_memory = 0; - printk(BIOS_DEBUG, "Setting initial Nothbridge registers....\n"); + printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n"); /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); - /* Set the value for Programable Attribute Map Registers + /* Set the value for Programmable Attribute Map Registers * Ideally, this should be R/W for as many ranges as possible. */ pci_write_config8(NORTHBRIDGE, PAM0, 0x30); |