diff options
Diffstat (limited to 'src/northbridge/intel/i440bx')
| -rw-r--r-- | src/northbridge/intel/i440bx/memmap.c | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 495ca8682a..084679ff4a 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -68,27 +68,20 @@ void *cbmem_top(void) return (void *)tom; } -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) +void fill_postcar_frame(struct postcar_frame *pcf) { - struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - run_postcar_phase(&pcf); } |