diff options
Diffstat (limited to 'src/northbridge/intel/i440bx')
| -rw-r--r-- | src/northbridge/intel/i440bx/Kconfig | 13 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.c | 6 |
2 files changed, 18 insertions, 1 deletions
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 696e884705..4de84d3472 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -22,3 +22,16 @@ config NORTHBRIDGE_INTEL_I440BX bool select HAVE_HIGH_TABLES +config SDRAMPWR_4DIMM + bool + depends on NORTHBRIDGE_INTEL_I440BX + default n + help + This option affects how the SDRAMC register is programmed. + Memory clock signals will not be routed properly if this option + is set wrong. + + If your board has 4 DIMM slots, you must use select this option, in + your Kconfig file of the board. On boards with 3 DIMM slots, + do _not_ select this option. + diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 3de2dd7021..43e2a45e99 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -292,7 +292,11 @@ static const long register_values[] = { * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ - SDRAMC + 0, 0x00, 0x00, +#if CONFIG_SDRAMPWR_4DIMM + SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ +#else + SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots.*/ +#endif SDRAMC + 1, 0x00, 0x00, /* PGPOL - Paging Policy Register |