4 files changed, 21 insertions, 4 deletions
diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc
index 16d702a24e..0c0a3c846d 100644
--- a/src/northbridge/intel/i440bx/Makefile.inc
+++ b/src/northbridge/intel/i440bx/Makefile.inc
@@ -20,3 +20,6 @@
 
 driver-y += northbridge.c
 
+romstage-y += raminit.c
+romstage-y += debug.c
+
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index 6f253bd941..d5748737b6 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -1,4 +1,6 @@
-static void dump_spd_registers(void)
+#include "raminit.h"
+
+void dump_spd_registers(void)
 {
 #if CONFIG_DEBUG_RAM_SETUP
 	int i;
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index ebcd368511..9a5968d592 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -21,7 +21,12 @@
 
 #include <spd.h>
 #include <delay.h>
+#include <stdint.h>
 #include <stdlib.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
 #include "i440bx.h"
 #include "raminit.h"
 
@@ -630,7 +635,7 @@ static void spd_enable_refresh(void)
 Public interface.
 -----------------------------------------------------------------------------*/
 
-static void sdram_set_registers(void)
+void sdram_set_registers(void)
 {
 	int i, max;
 	uint8_t reg;
@@ -956,7 +961,7 @@ static void set_dram_row_attributes(void)
 	PRINT_DEBUG("\n");
 }
 
-static void sdram_set_spd_registers(void)
+void sdram_set_spd_registers(void)
 {
 	/* Setup DRAM row boundary registers and other attributes. */
 	set_dram_row_attributes();
@@ -972,7 +977,7 @@ static void sdram_set_spd_registers(void)
 	pci_write_config8(NB, DRAMT, 0x03);
 }
 
-static void sdram_enable(void)
+void sdram_enable(void)
 {
 	int i;
 
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index d05f6fd8c9..18268a1e82 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -26,5 +26,12 @@
 
 /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
 #define DIMM_SPD_BASE	0x50
+ 
+/* Function prototypes. */
+int spd_read_byte(unsigned int device, unsigned int address);
+void sdram_set_registers(void);
+void sdram_set_spd_registers(void);
+void sdram_enable(void);
+void dump_spd_registers(void);
 
 #endif				/* RAMINIT_H */