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-rw-r--r--src/northbridge/intel/haswell/bootblock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 41f18be337..59c31aa672 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
- * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent
+ * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent
* non-explicit config accesses use MCFG. This code also assumes that
* bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using
- * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/