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-rw-r--r--src/northbridge/intel/haswell/acpi/hostbridge.asl5
-rw-r--r--src/northbridge/intel/haswell/northbridge.c9
2 files changed, 4 insertions, 10 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index bc1a1c8df1..d0faa7931c 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -182,11 +182,6 @@ Device (PDRC)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
-
-#if CONFIG(CHROMEOS_RAMOOPS)
- Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
-#endif
})
// Current Resource Settings
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 61ad23610e..c00c801ee1 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -14,6 +14,7 @@
#include <boot/tables.h>
#include <security/intel/txt/txt_register.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
#include "haswell.h"
@@ -335,11 +336,9 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
-#if CONFIG(CHROMEOS_RAMOOPS)
- reserved_ram_resource(dev, index++,
- CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
- CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
-#endif
+ if (CONFIG(CHROMEOS_RAMOOPS))
+ chromeos_reserve_ram_oops(dev, index++);
+
*resource_cnt = index;
}