diff options
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b98d88085e..1ec4cd1cb9 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -190,11 +190,9 @@ void intel_northbridge_haswell_finalize_smm(void); struct pei_data; -struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; const void *gpio_map; - const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 579eca791b..c3d9a1088a 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params) enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->gpio_map); /* Perform some early chipset initialization required * before RAM initialization can work |