2 files changed, 13 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 53c2f366c2..b57b28e632 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -543,6 +543,16 @@ static void northbridge_init(struct device *dev)
 	MCHBAR32(0x5500) = 0x00100001;
 }
 
+void *cbmem_top(void)
+{
+	u32 reg;
+
+	/* The top the reserve regions fall just below the TSEG region. */
+	reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
+
+	return (void *)(reg & ~((1 << 20) - 1));
+}
+
 static void northbridge_enable(device_t dev)
 {
 #if CONFIG_HAVE_ACPI_RESUME
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 9a9bb1c09f..c1095a7eb7 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -202,9 +202,10 @@ void sdram_initialize(struct pei_data *pei_data)
 	report_memory_config();
 }
 
-struct cbmem_entry *get_cbmem_toc(void)
+void *cbmem_top(void)
 {
-	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+	/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
+	return (void *)get_top_of_ram();
 }
 
 unsigned long get_top_of_ram(void)