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Diffstat (limited to 'src/northbridge/intel/haswell/romstage.c')
-rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 40b7b879d1..2961299e7d 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -87,6 +87,9 @@ void mainboard_romstage_entry(void) /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ pei_data.boot_mode = wake_from_s3 ? 2 : 0; + /* Obtain the SPD addresses from mainboard code */ + mb_get_spd_map(pei_data.spd_addresses); + /* Calculate unimplemented DIMM slots for each channel */ pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); |