diff options
Diffstat (limited to 'src/northbridge/intel/haswell/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/haswell/ram_calc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index bdf54d2435..3a63afcde6 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <cbmem.h> +#include <stage_cache.h> #include "haswell.h" static uintptr_t smm_region_start(void) @@ -34,3 +35,16 @@ void *cbmem_top(void) { return (void *)smm_region_start(); } + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} |