diff options
Diffstat (limited to 'src/northbridge/intel/haswell/memmap.c')
| -rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 74d9292c14..2e8addef97 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// Use simple device model for this file even in ramstage +/* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> @@ -30,7 +30,7 @@ static uintptr_t smm_region_start(void) * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignment. */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG); return tom & ~((1 << 20) - 1); } @@ -53,7 +53,6 @@ void fill_postcar_frame(struct postcar_frame *pcf) * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } |