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-rw-r--r--src/northbridge/intel/haswell/haswell.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index d8221a986b..b673f81543 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -32,7 +32,11 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#ifndef __ACPI__
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#include <southbridge/intel/lynxpoint/pch.h>