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Diffstat (limited to 'src/northbridge/intel/gm45/ram_calc.c')
-rw-r--r--src/northbridge/intel/gm45/ram_calc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 0e953419fe..5af3e16037 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -107,7 +107,7 @@ uintptr_t smm_region_start(void)
}
/* Depending of UMA and TSEG configuration, TSEG might start at any
- * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)