diff options
Diffstat (limited to 'src/northbridge/intel/gm45/pcie.c')
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 39791a62b8..ae34a11b5f 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -308,7 +308,7 @@ static void setup_rcrb(const int peg_enabled) /* Link1: component ID 1, link valid. */ EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = DEFAULT_DMIBAR; + EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; if (peg_enabled) /* Link2: link_valid. */ @@ -322,12 +322,12 @@ static void setup_rcrb(const int peg_enabled) /* Link1: target port 0, component id 2 (ICH), link valid. */ DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = DEFAULT_RCBA; + DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR; } void gm45_late_init(const stepping_t stepping) |