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Diffstat (limited to 'src/northbridge/intel/gm45/pcie.c')
-rw-r--r--src/northbridge/intel/gm45/pcie.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 88c3cee117..5a4999e4b0 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -217,7 +217,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29);
}
-
/*\ Setup ASPM on DMI \*/
/* Exit latencies should be checked to be supported by
@@ -232,7 +231,6 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
DMIBAR8(0x208 + 3) = 0;
DMIBAR32(0x208) &= ~(3 << 20);
-
/*\ Setup ASPM on PEG \*/
/*
* Maybe we just have to advertise ASPM through LCAP[11:10]
@@ -258,7 +256,6 @@ static void setup_rcrb(const int peg_enabled)
/* Link2: link_valid. */
EPBAR8(EPLE2D) |= (1 << 0); /* link valid */
-
/*\ RCRB setup: DMI Port \*/
/* Set component ID of MCH (1). */