diff options
Diffstat (limited to 'src/northbridge/intel/gm45/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 014de26bbb..7ff046e9f3 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -41,7 +41,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (!dev) return 0; @@ -95,7 +95,7 @@ static void mch_domain_read_resources(struct device *dev) pci_domain_read_resources(dev); - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config16(mch, D0F0_TOUUD); @@ -196,7 +196,7 @@ static void mch_domain_init(struct device *dev) { u32 reg32; - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); /* Enable SERR */ reg32 = pci_read_config32(mch, PCI_COMMAND); @@ -222,7 +222,7 @@ static const char *northbridge_acpi_name(const struct device *dev) void northbridge_write_smram(u8 smram) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (dev == NULL) die("could not find pci 00:00.0!\n"); @@ -309,7 +309,7 @@ static void gm45_init(void *const chip_info) } for (; fn >= 0; --fn) { const struct device *const d = - dev_find_slot(0, PCI_DEVFN(dev, fn)); + pcidev_on_root(dev, fn); if (!d || d->enabled) continue; const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); pci_write_config32(d0f0, D0F0_DEVEN, |