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Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/udelay.c')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/udelay.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/udelay.c b/src/northbridge/intel/fsp_sandybridge/udelay.c index d4821999d5..8f95595c12 100644 --- a/src/northbridge/intel/fsp_sandybridge/udelay.c +++ b/src/northbridge/intel/fsp_sandybridge/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h> /** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz */ void udelay(u32 us) |