diff options
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/fsp')
4 files changed, 242 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/Kconfig b/src/northbridge/intel/fsp_sandybridge/fsp/Kconfig new file mode 100644 index 0000000000..82e5361505 --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/fsp/Kconfig @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config SANDYBRIDGE_FSP_SPECIFIC_OPTIONS + def_bool y + select PLATFORM_USES_FSP1_0 + select USE_GENERIC_FSP_CAR_INC + +config FSP_FILE + string + default "../intel/fsp/ivybridge_bd82x6x/FvFsp.bin" if SOUTHBRIDGE_INTEL_FSP_BD82X6X + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_LOC + hex "Intel FSP Binary location in CBFS" + default 0xfff80000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with the Intel's BCT (tool). + + The Ivy Bridge Processor/Panther Point FSP is built with a preferred + base address of 0xFFF80000 diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc new file mode 100644 index 0000000000..282570351b --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +ramstage-y += chipset_fsp_util.c +romstage-y += chipset_fsp_util.c diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c new file mode 100644 index 0000000000..e9dad29f4c --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <bootstate.h> +#include <cbmem.h> +#include <device/device.h> +#include <southbridge_pci_devs.h> +#include <fsp_util.h> +#include "../chip.h" +#include <reset.h> + +#ifndef CONFIG_ENABLE_FSP_FAST_BOOT +# error "CONFIG_ENABLE_FSP_FAST_BOOT must be set." +#endif + +#ifdef __PRE_RAM__ + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) +static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) +{ + VPD_DATA_REGION *VpdDataRgnPtr; + UPD_DATA_REGION *UpdDataRgnPtr; + VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); + UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); + memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); +} + +static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) +{ + UpdData->HTEnable = TRUE; + UpdData->TurboEnable = FALSE; + UpdData->MemoryDownEnable = FALSE; + UpdData->FastBootEnable = CONFIG_ENABLE_FSP_FAST_BOOT; +} +#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) */ +const PLATFORM_CONFIG DefaultPlatformConfig = { + TRUE, /* Hyperthreading */ + FALSE, /* Turbo Mode */ + FALSE, /* Memory Down */ +#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) + TRUE, /* Fast Boot */ +#else + FALSE, /* Fast Boot */ +#endif /* CONFIG_ENABLE_FSP_FAST_BOOT */ +}; +#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) */ + +/* + * + * Call the FSP to do memory init. The FSP doesn't return to this function. + * The FSP returns to the romstage_main_continue(). + * + */ +void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, + FSP_INFO_HEADER *fsp_ptr) +{ + FSP_INIT_RT_BUFFER *pFspRtBuffer = FspInitParams->RtBufferPtr; +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) + UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr; +#else + MEM_CONFIG MemoryConfig; + memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG)); +#endif + FspInitParams->NvsBufferPtr = NULL; + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) + /* Initialize the UPD Data */ + GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); + ConfigureDefaultUpdData(fsp_upd_data); +#else + pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; + pFspRtBuffer->PlatformConfiguration.PlatformConfig = &DefaultPlatformConfig; +#endif + +#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) + /* Find the fastboot cache that was saved in the ROM */ + FspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); +#endif + + pFspRtBuffer->Common.BootMode = 0; +} + +/* The FSP returns here after the fsp_early_init call */ +void ChipsetFspReturnPoint(EFI_STATUS Status, + VOID *HobListPtr) +{ + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { + hard_reset(); + } + romstage_main_continue(Status, HobListPtr); +} + +#endif /* __PRE_RAM__ */ diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h new file mode 100644 index 0000000000..cb0434776b --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef CHIPSET_FSP_UTIL_H +#define CHIPSET_FSP_UTIL_H + +#include <fsptypes.h> +#include <fspfv.h> +#include <fspffs.h> +#include <fspapi.h> +#include <fspplatform.h> +#include <fspinfoheader.h> +#include <fsphob.h> +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) +#include <peifsp.h> +#include <fsp_vpd.h> +#endif + +#define FSP_RESERVE_MEMORY_SIZE 0x200000 + +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + + +/* + *The FSP Image ID is different for each platform's FSP and + * can be used to verify that the right FSP binary is loaded. + */ + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) +/* ST2-FSP0 */ +#define FSP_IMAGE_ID_DWORD0 0x2D325453 +#define FSP_IMAGE_ID_DWORD1 0x30505346 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) +/* CC2-FSP\0 */ +#define FSP_IMAGE_ID_DWORD0 0x2D324343 +#define FSP_IMAGE_ID_DWORD1 0x00505346 +#endif + +#ifdef __PRE_RAM__ +void main(FSP_INFO_HEADER *fsp_info_header); +void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr); +#endif + +#endif /* CHIPSET_FSP_UTIL_H */ |