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Diffstat (limited to 'src/northbridge/intel/e7505')
-rw-r--r--src/northbridge/intel/e7505/debug.c135
-rw-r--r--src/northbridge/intel/e7505/raminit.c18
2 files changed, 27 insertions, 126 deletions
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 3d6ca2a25e..cdf6e7ed17 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -15,12 +15,8 @@
void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
void print_pci_devices(void)
@@ -37,7 +33,7 @@ void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -48,24 +44,12 @@ void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
void dump_pci_devices(void)
@@ -105,98 +89,55 @@ void dump_pci_devices_on_bus(unsigned busn)
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( spd_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -204,24 +145,12 @@ void dump_smbus_registers(void)
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -229,31 +158,15 @@ void dump_io_resources(unsigned port)
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -262,23 +175,11 @@ void dump_io_resources(unsigned port)
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 909e740131..b758c610f1 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -42,9 +42,9 @@ Definitions:
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(MCHDEV)
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -605,7 +605,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -633,11 +633,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1379,13 +1379,13 @@ static void configure_e7501_dram_controller_mode(const struct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1767,7 +1767,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 22:17:02 +0000