diff options
Diffstat (limited to 'src/northbridge/ibm/cpc710/cpc710_pci.c')
-rw-r--r-- | src/northbridge/ibm/cpc710/cpc710_pci.c | 407 |
1 files changed, 108 insertions, 299 deletions
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c index bed8aeab09..0083ae6480 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.c +++ b/src/northbridge/ibm/cpc710/cpc710_pci.c @@ -1,309 +1,118 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ +#include <stdint.h> +#include <arch/io.h> +#include "cpc710.h" +#include "cpc710_pci.h" -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <pci.h> +extern void setCPC710(uint32_t, uint32_t); -#include "hardware.h" -#include "pcippc2.h" - -struct pci_controller local_hose, cpci_hose; - -static u32 cpc710_mapped_ram; - - /* Enable PCI retry timeouts - */ -void cpc710_pci_enable_timeout (void) +void +setCPC710PCI32_16(uint32_t addr, uint16_t data) { - out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x32000000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x50000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x32000000); - iobarrier_rw(); + out_le16((unsigned short *)(CPC710_BRIDGE_CPCI_PHYS + addr), data); } -void cpc710_pci_init (void) +void +setCPC710PCI32_32(uint32_t addr, uint32_t data) { - u32 sdram_size = pcippc2_sdram_size(); - - cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ? - sdram_size : PCI_MEMORY_MAXSIZE; - - /* Select the local PCI - */ - out32(REG(CPC0, PCICNFR), 0x80000002); - iobarrier_rw(); - - out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS); - iobarrier_rw(); - - /* Enable PCI bridge address decoding - */ - out32(REG(CPC0, PCIENB), 0x80000000); - iobarrier_rw(); - - /* Select the CPCI bridge - */ - out32(REG(CPC0, PCICNFR), 0x80000003); - iobarrier_rw(); - - out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS); - iobarrier_rw(); - - /* Enable PCI bridge address decoding - */ - out32(REG(CPC0, PCIENB), 0x80000000); - iobarrier_rw(); - - /* Disable configuration accesses - */ - out32(REG(CPC0, PCICNFR), 0x80000000); - iobarrier_rw(); - - /* Initialise the local PCI - */ - out32(BRIDGE(LOCAL, CRR), 0x7c000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PCIDG), 0x40000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS); - out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS); - out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS); - out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS); - out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PR), 0x00ffe000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, ACR), 0xfe000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24); - out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24); - out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); - iobarrier_rw(); - - /* Initialise the CPCI bridge - */ - out32(BRIDGE(CPCI, CRR), 0x7c000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PCIDG), 0xC0000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS); - out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS); - out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE); - iobarrier_rw(); - out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS); - out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS); - out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE); - iobarrier_rw(); - out32(BRIDGE(CPCI, PR), 0x80ffe000); - iobarrier_rw(); - out32(BRIDGE(CPCI, ACR), 0xdf000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24); - out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24); - out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); - iobarrier_rw(); - - /* Local PCI - */ - - out32(BRIDGE(LOCAL, CFGADDR), 0x04000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x56010000); - iobarrier_rw(); - - out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); - iobarrier_rw(); - - /* Set bus and subbus numbers - */ - out32(BRIDGE(LOCAL, CFGADDR), 0x40000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); - iobarrier_rw(); - - out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); - iobarrier_rw(); - /* PCI retry timeouts will be enabled later - */ - out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); - iobarrier_rw(); - - /* CPCI - */ - - /* Set bus and subbus numbers - */ - out32(BRIDGE(CPCI, CFGADDR), 0x40000080); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x01010000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x04000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x56010000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x0c000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); - iobarrier_rw(); - - /* Write to the PSBAR */ - out32(BRIDGE(CPCI, CFGADDR), 0x10000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS)); - iobarrier_rw(); - - /* Set bus and subbus numbers - */ - out32(BRIDGE(CPCI, CFGADDR), 0x40000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x50000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x32000000); - /* PCI retry timeouts will be enabled later - */ - out32(BRIDGE(CPCI, CFGDATA), 0x00000000); - iobarrier_rw(); - - /* Remove reset on the PCI buses - */ - out32(BRIDGE(LOCAL, CRR), 0xfc000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, CRR), 0xfc000000); - iobarrier_rw(); - - local_hose.first_busno = 0; - local_hose.last_busno = 0xff; - - /* System memory space */ - pci_set_region(local_hose.regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHYS, - PCI_MEMORY_MAXSIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(local_hose.regions + 1, - BRIDGE_LOCAL_MEM_BUS, - BRIDGE_LOCAL_MEM_PHYS, - BRIDGE_LOCAL_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(local_hose.regions + 2, - BRIDGE_LOCAL_IO_BUS, - BRIDGE_LOCAL_IO_PHYS, - BRIDGE_LOCAL_IO_SIZE, - PCI_REGION_IO); - - local_hose.region_count = 3; - - pci_setup_indirect(&local_hose, - BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR, - BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA); - - pci_register_hose(&local_hose); - - /* Initialize PCI32 bus registers */ - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_BUS_NUMBER, - local_hose.first_busno); - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - local_hose.last_busno); - - local_hose.last_busno = pci_hose_scan(&local_hose); - - /* Write out correct max subordinate bus number for local hose */ - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - local_hose.last_busno); - - cpci_hose.first_busno = local_hose.last_busno + 1; - cpci_hose.last_busno = 0xff; - - /* System memory space */ - pci_set_region(cpci_hose.regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHYS, - PCI_MEMORY_MAXSIZE, - PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(cpci_hose.regions + 1, - BRIDGE_CPCI_MEM_BUS, - BRIDGE_CPCI_MEM_PHYS, - BRIDGE_CPCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(cpci_hose.regions + 2, - BRIDGE_CPCI_IO_BUS, - BRIDGE_CPCI_IO_PHYS, - BRIDGE_CPCI_IO_SIZE, - PCI_REGION_IO); - - cpci_hose.region_count = 3; - - pci_setup_indirect(&cpci_hose, - BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR, - BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA); - - pci_register_hose(&cpci_hose); + out_le32((unsigned *)(CPC710_BRIDGE_CPCI_PHYS + addr), data); +} - /* Initialize PCI64 bus registers */ - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_BUS_NUMBER, - cpci_hose.first_busno); - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - cpci_hose.last_busno); +void +setCPC710PCI64_16(uint16_t addr, uint16_t data) +{ + out_le16((unsigned short *)(CPC710_BRIDGE_LOCAL_PHYS + addr), data); +} - cpci_hose.last_busno = pci_hose_scan(&cpci_hose); +void +setCPC710PCI64_32(uint32_t addr, uint32_t data) +{ + out_le32((unsigned *)(CPC710_BRIDGE_LOCAL_PHYS + addr), data); +} - /* Write out correct max subordinate bus number for cpci hose */ - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - cpci_hose.last_busno); +void +cpc710_pci_init(void) +{ + /* Enable PCI32 */ + setCPC710(CPC710_CPC0_PCICNFR, 0x80000002); /* activate PCI32 config */ + setCPC710(CPC710_CPC0_PCIBAR, CPC710_BRIDGE_CPCI_PHYS); /* PCI32 base address */ + setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */ + setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */ + + /* Reset PCI Status register */ + setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000006); + setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0xffff); + + /* Configure bus number */ + setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000040); + setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0x0000); + + /* Set PCI configuration registers */ + setCPC710PCI32_32(CPC710_BRIDGE_PCIDG, 0x40000000); + setCPC710PCI32_32(CPC710_BRIDGE_PIBAR, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_PMBAR, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_PR, 0xa000c000); + setCPC710PCI32_32(CPC710_BRIDGE_ACR, 0xfc000000); + setCPC710PCI32_32(CPC710_BRIDGE_MSIZE, 0xf8000000); /* 128Mb */ + setCPC710PCI32_32(CPC710_BRIDGE_IOSIZE, 0xf8000000); /* 128Mb */ + setCPC710PCI32_32(CPC710_BRIDGE_SMBAR, 0xc0000000); + setCPC710PCI32_32(CPC710_BRIDGE_SIBAR, 0x80000000); + setCPC710PCI32_32(CPC710_BRIDGE_CTLRW, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_PSSIZE, 0x00000080); + setCPC710PCI32_32(CPC710_BRIDGE_BARPS, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_PSBAR, 0x00000080); + setCPC710PCI32_32(CPC710_BRIDGE_BPMDLK, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_TPMDLK, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_BIODLK, 0x00000000); + setCPC710PCI32_32(CPC710_BRIDGE_TIODLK, 0x00000000); + + /* Enable address space */ + setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000004); + setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0xfda7); + + setCPC710PCI32_32(CPC710_BRIDGE_CRR, 0xfc000000); + + /* Enable PCI64 */ + setCPC710(CPC710_CPC0_PCICNFR, 0x80000003); /* activate PCI64 config */ + setCPC710(CPC710_CPC0_PCIBAR, CPC710_BRIDGE_LOCAL_PHYS); /* PCI64 base address */ + setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */ + setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */ + + /* Reset PCI Status register */ + setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000006); + setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0xffff); + + /* Reset G_INT[A-D] bits in INT_RESET */ + setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000068); + setCPC710PCI64_32(CPC710_BRIDGE_CFGDATA, 0x0000000f); + + /* Configure bus number BUSNO=1, SUBNO=1 */ + setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000040); + setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0x0101); + + /* Set PCI configuration registers */ + setCPC710PCI64_32(CPC710_BRIDGE_PSEA, 0x00000000); + setCPC710PCI64_32(CPC710_BRIDGE_PCIDG, 0xc0000000); + setCPC710PCI64_32(CPC710_BRIDGE_PIBAR, 0x00000000); + setCPC710PCI64_32(CPC710_BRIDGE_PMBAR, 0x00000000); + setCPC710PCI64_32(CPC710_BRIDGE_PR, 0x80008000); + setCPC710PCI64_32(CPC710_BRIDGE_ACR, 0xff000000); + setCPC710PCI64_32(CPC710_BRIDGE_MSIZE, 0xf8000000); /* 128Mb */ + setCPC710PCI64_32(CPC710_BRIDGE_IOSIZE, 0xf8000000); /* 128Mb */ + setCPC710PCI64_32(CPC710_BRIDGE_SMBAR, 0xc8000000); + setCPC710PCI64_32(CPC710_BRIDGE_SIBAR, 0x88000000); + setCPC710PCI64_32(CPC710_BRIDGE_CTLRW, 0x02000000); + setCPC710PCI64_32(CPC710_BRIDGE_PSSIZE, 0x00000080); + + /* Config PSBAR for PCI64 */ + setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000010); + setCPC710PCI64_32(CPC710_BRIDGE_CFGDATA, 0x80000000); + + setCPC710PCI64_32(CPC710_BRIDGE_BARPS, 0x00000000); + setCPC710PCI64_32(CPC710_BRIDGE_INTSET, 0x00000000); + + /* Enable address space */ + setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80010004); + setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0xfda7); + + setCPC710PCI64_32(CPC710_BRIDGE_CRR, 0xfc000000); } |