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-rw-r--r--src/northbridge/amd/agesa/Makefile.inc1
-rw-r--r--src/northbridge/amd/agesa/family15/Kconfig40
-rw-r--r--src/northbridge/amd/agesa/family15/Makefile.inc21
-rw-r--r--src/northbridge/amd/agesa/family15/amdfam10.h97
-rw-r--r--src/northbridge/amd/agesa/family15/chip.h45
-rw-r--r--src/northbridge/amd/agesa/family15/dimmSpd.c61
-rw-r--r--src/northbridge/amd/agesa/family15/northbridge.c1053
-rw-r--r--src/northbridge/amd/agesa/family15/reset_test.h49
-rw-r--r--src/northbridge/amd/agesa/family15/state_machine.c78
9 files changed, 0 insertions, 1445 deletions
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index b6ac7a4354..338f99a637 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y)
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig
deleted file mode 100644
index c895b5d7ab..0000000000
--- a/src/northbridge/amd/agesa/family15/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-config NORTHBRIDGE_AMD_AGESA_FAMILY15
- bool
- select HAVE_DEBUG_RAM_SETUP
- select HAVE_DEBUG_SMBUS
- select HYPERTRANSPORT_PLUGIN_SUPPORT
-
-if NORTHBRIDGE_AMD_AGESA_FAMILY15
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x100000
-
-config HW_MEM_HOLE_SIZE_AUTO_INC
- bool
- default n
-
-config MMCONF_BASE_ADDRESS
- hex
- default 0xF8000000
-
-config MMCONF_BUS_NUMBER
- int
- default 64
-
-endif # NORTHBRIDGE_AMD_AGESA_FAMILY15
diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc
deleted file mode 100644
index 3021ef48da..0000000000
--- a/src/northbridge/amd/agesa/family15/Makefile.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-romstage-y += dimmSpd.c
-
-ramstage-y += northbridge.c
-
-romstage-y += state_machine.c
-ramstage-y += state_machine.c
diff --git a/src/northbridge/amd/agesa/family15/amdfam10.h b/src/northbridge/amd/agesa/family15/amdfam10.h
deleted file mode 100644
index 27f78a3331..0000000000
--- a/src/northbridge/amd/agesa/family15/amdfam10.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMDFAM10_H
-#define AMDFAM10_H
-
-#include <cpu/x86/msr.h>
-
-#define HWCR_MSR 0xC0010015
-#define NB_CFG_MSR 0xC001001f
-#define LS_CFG_MSR 0xC0011020
-#define IC_CFG_MSR 0xC0011021
-#define DC_CFG_MSR 0xC0011022
-#define BU_CFG_MSR 0xC0011023
-#define BU_CFG2_MSR 0xC001102A
-
-#define CPU_ID_FEATURES_MSR 0xC0011004
-#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
-
-/* Definitions of various FAM10 registers */
-/* Function 0 */
-#define HT_TRANSACTION_CONTROL 0x68
-#define HTTC_DIS_RD_B_P (1 << 0)
-#define HTTC_DIS_RD_DW_P (1 << 1)
-#define HTTC_DIS_WR_B_P (1 << 2)
-#define HTTC_DIS_WR_DW_P (1 << 3)
-#define HTTC_DIS_MTS (1 << 4)
-#define HTTC_CPU1_EN (1 << 5)
-#define HTTC_CPU_REQ_PASS_PW (1 << 6)
-#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7)
-#define HTTC_DIS_P_MEM_C (1 << 8)
-#define HTTC_DIS_RMT_MEM_C (1 << 9)
-#define HTTC_DIS_FILL_P (1 << 10)
-#define HTTC_RSP_PASS_PW (1 << 11)
-#define HTTC_BUF_REL_PRI_SHIFT 13
-#define HTTC_BUF_REL_PRI_MASK 3
-#define HTTC_BUF_REL_PRI_64 0
-#define HTTC_BUF_REL_PRI_16 1
-#define HTTC_BUF_REL_PRI_8 2
-#define HTTC_BUF_REL_PRI_2 3
-#define HTTC_LIMIT_CLDT_CFG (1 << 15)
-#define HTTC_LINT_EN (1 << 16)
-#define HTTC_APIC_EXT_BRD_CST (1 << 17)
-#define HTTC_APIC_EXT_ID (1 << 18)
-#define HTTC_APIC_EXT_SPUR (1 << 19)
-#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20)
-#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21
-#define HTTC_DS_NP_REQ_LIMIT_MASK 3
-#define HTTC_DS_NP_REQ_LIMIT_NONE 0
-#define HTTC_DS_NP_REQ_LIMIT_1 1
-#define HTTC_DS_NP_REQ_LIMIT_4 2
-#define HTTC_DS_NP_REQ_LIMIT_8 3
-
-/* Function 1 */
-
-/* Function 2 */
-
-/* Function 3 */
-
-
-/* Function 5 for FBDIMM */
-#define LinkConnected (1 << 0)
-#define InitComplete (1 << 1)
-#define NonCoherent (1 << 2)
-#define ConnectionPending (1 << 4)
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 8
- #if CONFIG_MAX_PHYSICAL_CPUS > 32
- #define NODE_NUMS 64
- #else
- #define NODE_NUMS 32
- #endif
-#else
- #define NODE_NUMS 8
-#endif
-
-#ifdef __PRE_RAM__
-#if NODE_NUMS == 64
- #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
- #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
-#endif
-
-#endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h
deleted file mode 100644
index fdc0c2bdea..0000000000
--- a/src/northbridge/amd/agesa/family15/chip.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _NB_AGESA_CHIP_H_
-#define _NB_AGESA_CHIP_H_
-
-struct northbridge_amd_agesa_family15_config
-{
- /*
- * Here are a couple of examples of how this would be put into the
- * devicetree.cb file. Note the array is oversized to support different
- * configurations of server boards.
- * This should be placed after the device pci 18.x statements.
- *
- * Example: AMD Dinar
- * register "spdAddrLookup" = "
- * { // Use 8-bit SPD addresses here
- * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3
- * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3
- * }"
- * Example: Tyan S8226
- * register "spdAddrLookup" = "
- * { // Use 8-bit SPD addresses here
- * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0
- * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1
- * }"
- *
- */
-
- u8 spdAddrLookup[8][4][4];
-};
-
-#endif
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c
deleted file mode 100644
index 2e33c0de56..0000000000
--- a/src/northbridge/amd/agesa/family15/dimmSpd.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <stdlib.h>
-#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
-
-/* warning: Porting.h includes an open #pragma pack(1) */
-#include "Porting.h"
-#include "AGESA.h"
-#include "chip.h"
-
-#include <northbridge/amd/agesa/dimmSpd.h>
-
-/**
- * Gets the SMBus address for an SPD from the array in devicetree.cb
- * then read the SPD into the supplied buffer.
- */
-AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
-{
- UINT8 spdAddress;
-
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
- if (dev == NULL)
- return AGESA_ERROR;
-
- DEVTREE_CONST struct northbridge_amd_agesa_family15_config *config = dev->chip_info;
- if (config == NULL)
- return AGESA_ERROR;
-
- if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
- return AGESA_ERROR;
- if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
- return AGESA_ERROR;
- if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
- return AGESA_ERROR;
-
- spdAddress = config->spdAddrLookup
- [info->SocketId][info->MemChannelId][info->DimmId];
-
- if (spdAddress == 0)
- return AGESA_ERROR;
-
- int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 256);
- if (err)
- return AGESA_ERROR;
- return AGESA_SUCCESS;
-}
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
deleted file mode 100644
index 2ef652d45d..0000000000
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ /dev/null
@@ -1,1053 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/hypertransport.h>
-#include <stdlib.h>
-#include <string.h>
-#include <lib.h>
-#include <cpu/cpu.h>
-#include <cbmem.h>
-
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/mtrr.h>
-
-#include <Porting.h>
-#include <AGESA.h>
-#include <Options.h>
-#include <Topology.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include "sb_cimx.h"
-
-#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
-
-typedef struct dram_base_mask {
- u32 base; //[47:27] at [28:8]
- u32 mask; //[47:27] at [28:8] and enable at bit 0
-} dram_base_mask_t;
-
-static unsigned node_nums;
-static unsigned sblink;
-static device_t __f0_dev[MAX_NODE_NUMS];
-static device_t __f1_dev[MAX_NODE_NUMS];
-static device_t __f2_dev[MAX_NODE_NUMS];
-static device_t __f4_dev[MAX_NODE_NUMS];
-static unsigned fx_devs = 0;
-
-static dram_base_mask_t get_dram_base_mask(u32 nodeid)
-{
- device_t dev;
- dram_base_mask_t d;
- dev = __f1_dev[0];
- u32 temp;
- temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
- d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
- temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
- d.mask |= temp << 21;
- temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
- d.mask |= (temp & 1); // enable bit
- d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
- temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
- d.base |= temp << 21;
- return d;
-}
-
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
- u32 io_min, u32 io_max)
-{
- u32 i;
- u32 tempreg;
- /* io range allocation */
- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
- for (i = 0; i < node_nums; i++)
- pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
- for (i = 0; i < node_nums; i++)
- pci_write_config32(__f1_dev[i], reg, tempreg);
-}
-
-static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
-{
- u32 i;
- u32 tempreg;
- /* io range allocation */
- tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
- for (i = 0; i < nodes; i++)
- pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i = 0; i < node_nums; i++)
- pci_write_config32(__f1_dev[i], reg, tempreg);
-}
-
-static device_t get_node_pci(u32 nodeid, u32 fn)
-{
-#if MAX_NODE_NUMS + CONFIG_CDB >= 32
- if ((CONFIG_CDB + nodeid) < 32) {
- return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
- } else {
- return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
- }
-#else
- return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
-#endif
-}
-
-static void get_fx_devs(void)
-{
- int i;
- for (i = 0; i < MAX_NODE_NUMS; i++) {
- __f0_dev[i] = get_node_pci(i, 0);
- __f1_dev[i] = get_node_pci(i, 1);
- __f2_dev[i] = get_node_pci(i, 2);
- __f4_dev[i] = get_node_pci(i, 4);
- if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
- fx_devs = i+1;
- }
- if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
- die("Cannot find 0:0x18.[0|1]\n");
- }
- printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
-}
-
-static u32 f1_read_config32(unsigned reg)
-{
- if (fx_devs == 0)
- get_fx_devs();
- return pci_read_config32(__f1_dev[0], reg);
-}
-
-static void f1_write_config32(unsigned reg, u32 value)
-{
- int i;
- if (fx_devs == 0)
- get_fx_devs();
- for (i = 0; i < fx_devs; i++) {
- device_t dev;
- dev = __f1_dev[i];
- if (dev && dev->enabled) {
- pci_write_config32(dev, reg, value);
- }
- }
-}
-
-static u32 amdfam15_nodeid(device_t dev)
-{
-#if MAX_NODE_NUMS == 64
- unsigned busn;
- busn = dev->bus->secondary;
- if (busn != CONFIG_CBB) {
- return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
- } else {
- return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
- }
-
-#else
- return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
-#endif
-}
-
-static void set_vga_enable_reg(u32 nodeid, u32 linkn)
-{
- u32 val;
-
- val = 1 | (nodeid << 4) | (linkn << 12);
- /* it will routing
- * (1)mmio 0xa0000:0xbffff
- * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
- */
- f1_write_config32(0xf4, val);
-
-}
-
-/**
- * @return
- * @retval 2 resoure does not exist, usable
- * @retval 0 resource exists, not usable
- * @retval 1 resource exist, resource has been allocated before
- */
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
- unsigned goal_link)
-{
- struct resource *res;
- unsigned nodeid, link = 0;
- int result;
- res = 0;
- for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
- device_t dev;
- dev = __f0_dev[nodeid];
- if (!dev)
- continue;
- for (link = 0; !res && (link < 8); link++) {
- res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
- }
- }
- result = 2;
- if (res) {
- result = 0;
- if ((goal_link == (link - 1)) &&
- (goal_nodeid == (nodeid - 1)) &&
- (res->flags <= 1)) {
- result = 1;
- }
- }
- return result;
-}
-
-static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link)
-{
- struct resource *resource;
- u32 free_reg, reg;
- resource = 0;
- free_reg = 0;
- for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
- int result;
- result = reg_useable(reg, dev, nodeid, link);
- if (result == 1) {
- /* I have been allocated this one */
- break;
- }
- else if (result > 1) {
- /* I have a free register pair */
- free_reg = reg;
- }
- }
- if (reg > 0xd8) {
- reg = free_reg; // if no free, the free_reg still be 0
- }
-
- resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
-
- return resource;
-}
-
-static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link)
-{
- struct resource *resource;
- u32 free_reg, reg;
- resource = 0;
- free_reg = 0;
- for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
- int result;
- result = reg_useable(reg, dev, nodeid, link);
- if (result == 1) {
- /* I have been allocated this one */
- break;
- }
- else if (result > 1) {
- /* I have a free register pair */
- free_reg = reg;
- }
- }
- if (reg > 0xb8) {
- reg = free_reg;
- }
-
- resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
- return resource;
-}
-
-static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
-{
- struct resource *resource;
-
- /* Initialize the io space constraints on the current bus */
- resource = amdfam15_find_iopair(dev, nodeid, link);
- if (resource) {
- u32 align;
- align = log2(HT_IO_HOST_ALIGN);
- resource->base = 0;
- resource->size = 0;
- resource->align = align;
- resource->gran = align;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
- }
-
- /* Initialize the prefetchable memory constraints on the current bus */
- resource = amdfam15_find_mempair(dev, nodeid, link);
- if (resource) {
- resource->base = 0;
- resource->size = 0;
- resource->align = log2(HT_MEM_HOST_ALIGN);
- resource->gran = log2(HT_MEM_HOST_ALIGN);
- resource->limit = 0xffffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- resource->flags |= IORESOURCE_BRIDGE;
- }
-
- /* Initialize the memory constraints on the current bus */
- resource = amdfam15_find_mempair(dev, nodeid, link);
- if (resource) {
- resource->base = 0;
- resource->size = 0;
- resource->align = log2(HT_MEM_HOST_ALIGN);
- resource->gran = log2(HT_MEM_HOST_ALIGN);
- resource->limit = 0xffffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
- }
-
-}
-
-static void nb_read_resources(device_t dev)
-{
- u32 nodeid;
- struct bus *link;
-
- nodeid = amdfam15_nodeid(dev);
- for (link = dev->link_list; link; link = link->next) {
- if (link->children) {
- amdfam15_link_read_bases(dev, nodeid, link->link_num);
- }
- }
-
- /*
- * This MMCONF resource must be reserved in the PCI domain.
- * It is not honored by the coreboot resource allocator if it is in
- * the CPU_CLUSTER.
- */
- mmconf_resource(dev, 0xc0010058);
-}
-
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
-{
- resource_t rbase, rend;
- unsigned reg, link_num;
- char buf[50];
-
- /* Make certain the resource has actually been set */
- if (!(resource->flags & IORESOURCE_ASSIGNED)) {
- return;
- }
-
- /* If I have already stored this resource don't worry about it */
- if (resource->flags & IORESOURCE_STORED) {
- return;
- }
-
- /* Only handle PCI memory and IO resources */
- if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
- return;
-
- /* Ensure I am actually looking at a resource of function 1 */
- if ((resource->index & 0xffff) < 0x1000) {
- return;
- }
- /* Get the base address */
- rbase = resource->base;
-
- /* Get the limit (rounded up) */
- rend = resource_end(resource);
-
- /* Get the register and link */
- reg = resource->index & 0xfff; // 4k
- link_num = IOINDEX_LINK(resource->index);
-
- if (resource->flags & IORESOURCE_IO) {
- set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
- }
- else if (resource->flags & IORESOURCE_MEM) {
- set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8]
- }
- resource->flags |= IORESOURCE_STORED;
- snprintf(buf, sizeof(buf), " <node %x link %x>",
- nodeid, link_num);
- report_resource_stored(dev, resource, buf);
-}
-
-/**
- * I tried to reuse the resource allocation code in set_resource()
- * but it is too difficult to deal with the resource allocation magic.
- */
-
-static void create_vga_resource(device_t dev, unsigned nodeid)
-{
- struct bus *link;
-
- /* find out which link the VGA card is connected,
- * we only deal with the 'first' vga card */
- for (link = dev->link_list; link; link = link->next) {
- if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
- extern device_t vga_pri; // the primary vga device, defined in device.c
- printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
- link->secondary,link->subordinate);
- /* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary) &&
- (vga_pri->bus->secondary <= link->subordinate))
-#endif
- break;
- }
- }
-
- /* no VGA card installed */
- if (link == NULL)
- return;
-
- printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
- set_vga_enable_reg(nodeid, sblink);
-}
-
-static void nb_set_resources(device_t dev)
-{
- unsigned nodeid;
- struct bus *bus;
- struct resource *res;
-
- /* Find the nodeid */
- nodeid = amdfam15_nodeid(dev);
-
- create_vga_resource(dev, nodeid); //TODO: do we need this?
-
- /* Set each resource we have found */
- for (res = dev->resource_list; res; res = res->next) {
- set_resource(dev, res, nodeid);
- }
-
- for (bus = dev->link_list; bus; bus = bus->next) {
- if (bus->children) {
- assign_resources(bus);
- }
- }
-}
-
-static void scan_chains(device_t dev)
-{
- unsigned nodeid;
- struct bus *link;
- device_t io_hub = NULL;
- u32 next_unitid = 0x18;
-
- nodeid = amdfam15_nodeid(dev);
- if (nodeid == 0) {
- ASSERT(dev->bus->secondary == 0);
- for (link = dev->link_list; link; link = link->next) {
- if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */
- io_hub = link->children;
- if (!io_hub || !io_hub->enabled) {
- die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
- }
- /* Now that nothing is overlapping it is safe to scan the children. */
- pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7);
- }
- }
- }
-}
-
-
-static unsigned long acpi_fill_hest(acpi_hest_t *hest)
-{
- void *addr, *current;
-
- /* Skip the HEST header. */
- current = (void *)(hest + 1);
-
- addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
- if (addr != NULL)
- current += acpi_create_hest_error_source(hest, current, 0,
- addr + 2, *(UINT16 *)addr - 2);
-
- addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
- if (addr != NULL)
- current += acpi_create_hest_error_source(hest, current, 1,
- addr + 2, *(UINT16 *)addr - 2);
-
- return (unsigned long)current;
-}
-
-static void northbridge_fill_ssdt_generator(device_t device)
-{
- msr_t msr;
- char pscope[] = "\\_SB.PCI0";
-
- acpigen_write_scope(pscope);
- msr = rdmsr(TOP_MEM);
- acpigen_write_name_dword("TOM1", msr.lo);
- msr = rdmsr(TOP_MEM2);
- /*
- * Since XP only implements parts of ACPI 2.0, we can't use a qword
- * here.
- * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
- * slide 22ff.
- * Shift value right by 20 bit to make it fit into 32bit,
- * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
- */
- acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
- acpigen_pop_len();
-}
-
-static unsigned long agesa_write_acpi_tables(device_t device,
- unsigned long current,
- acpi_rsdp_t *rsdp)
-{
- acpi_srat_t *srat;
- acpi_slit_t *slit;
- acpi_header_t *ssdt;
- acpi_header_t *alib;
- acpi_hest_t *hest;
-
- /* HEST */
- current = ALIGN(current, 8);
- hest = (acpi_hest_t *)current;
- acpi_write_hest((void *)current, acpi_fill_hest);
- acpi_add_table(rsdp, (void *)current);
- current += ((acpi_header_t *)current)->length;
-
- /* SRAT */
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
- srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
- if (srat != NULL) {
- memcpy((void *)current, srat, srat->header.length);
- srat = (acpi_srat_t *) current;
- current += srat->header.length;
- acpi_add_table(rsdp, srat);
- }
-
- /* SLIT */
- current = ALIGN(current, 8);
- printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
- slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
- if (slit != NULL) {
- memcpy((void *)current, slit, slit->header.length);
- slit = (acpi_slit_t *) current;
- current += slit->header.length;
- acpi_add_table(rsdp, slit);
- }
-
- /* SSDT */
- current = ALIGN(current, 16);
- printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
- alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
- if (alib != NULL) {
- memcpy((void *)current, alib, alib->length);
- alib = (acpi_header_t *) current;
- current += alib->length;
- acpi_add_table(rsdp, (void *)alib);
- } else {
- printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
- }
-
- /* The DSDT needs additional work for the AGESA SSDT Pstate table */
- /* Keep the comment for a while. */
- current = ALIGN(current, 16);
- printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
- ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
- if (ssdt != NULL) {
- memcpy((void *)current, ssdt, ssdt->length);
- ssdt = (acpi_header_t *) current;
- current += ssdt->length;
- acpi_add_table(rsdp,ssdt);
- } else {
- printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
- }
-
- return current;
-}
-
-
-static struct device_operations northbridge_operations = {
- .read_resources = nb_read_resources,
- .set_resources = nb_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = DEVICE_NOOP,
- .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
- .write_acpi_tables = agesa_write_acpi_tables,
- .scan_bus = scan_chains,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver family15_northbridge __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT,
-};
-
-static const struct pci_driver family10_northbridge __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_10H_NB_HT,
-};
-
-struct chip_operations northbridge_amd_agesa_family15_ops = {
- CHIP_NAME("AMD FAM15 Northbridge")
- .enable_dev = 0,
-};
-
-static void domain_read_resources(device_t dev)
-{
- unsigned reg;
-
- /* Find the already assigned resource pairs */
- get_fx_devs();
- for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
- u32 base, limit;
- base = f1_read_config32(reg);
- limit = f1_read_config32(reg + 0x04);
- /* Is this register allocated? */
- if ((base & 3) != 0) {
- unsigned nodeid, reg_link;
- device_t reg_dev;
- if (reg < 0xc0) { // mmio
- nodeid = (limit & 0xf) + (base&0x30);
- } else { // io
- nodeid = (limit & 0xf) + ((base>>4)&0x30);
- }
- reg_link = (limit >> 4) & 7;
- reg_dev = __f0_dev[nodeid];
- if (reg_dev) {
- /* Reserve the resource */
- struct resource *res;
- res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
- if (res) {
- res->flags = 1;
- }
- }
- }
- }
- /* FIXME: do we need to check extend conf space?
- I don't believe that much preset value */
-
- pci_domain_read_resources(dev);
-}
-
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-struct hw_mem_hole_info {
- unsigned hole_startk;
- int node_id;
-};
-static struct hw_mem_hole_info get_hw_mem_hole_info(void)
-{
- struct hw_mem_hole_info mem_hole;
- int i;
- mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
- mem_hole.node_id = -1;
- for (i = 0; i < node_nums; i++) {
- dram_base_mask_t d;
- u32 hole;
- d = get_dram_base_mask(i);
- if (!(d.mask & 1)) continue; // no memory on this node
- hole = pci_read_config32(__f1_dev[i], 0xf0);
- if (hole & 1) { // we find the hole
- mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
- mem_hole.node_id = i; // record the node No with hole
- break; // only one hole
- }
- }
-
- /* We need to double check if there is special set on base reg and limit reg
- * are not continuous instead of hole, it will find out its hole_startk.
- */
- if (mem_hole.node_id == -1) {
- resource_t limitk_pri = 0;
- for (i = 0; i < node_nums; i++) {
- dram_base_mask_t d;
- resource_t base_k, limit_k;
- d = get_dram_base_mask(i);
- if (!(d.base & 1)) continue;
- base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
- if (base_k > 4 *1024 * 1024) break; // don't need to go to check
- if (limitk_pri != base_k) { // we find the hole
- mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
- mem_hole.node_id = i;
- break; //only one hole
- }
- limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
- limitk_pri = limit_k;
- }
- }
- return mem_hole;
-}
-#endif
-
-static void domain_set_resources(device_t dev)
-{
- unsigned long mmio_basek;
- u32 pci_tolm;
- int i, idx;
- struct bus *link;
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
- struct hw_mem_hole_info mem_hole;
- u32 reset_memhole = 1;
-#endif
-
- pci_tolm = 0xffffffffUL;
- for (link = dev->link_list; link; link = link->next) {
- pci_tolm = find_pci_tolm(link);
- }
-
- // FIXME handle interleaved nodes. If you fix this here, please fix
- // amdk8, too.
- mmio_basek = pci_tolm >> 10;
- /* Round mmio_basek to something the processor can support */
- mmio_basek &= ~((1 << 6) -1);
-
- // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
- // MMIO hole. If you fix this here, please fix amdk8, too.
- /* Round the mmio hole to 64M */
- mmio_basek &= ~((64*1024) - 1);
-
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
- /* if the hw mem hole is already set in raminit stage, here we will compare
- * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
- * use hole_basek as mmio_basek and we don't need to reset hole.
- * otherwise We reset the hole to the mmio_basek
- */
-
- mem_hole = get_hw_mem_hole_info();
-
- // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
- if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
- mmio_basek = mem_hole.hole_startk;
- reset_memhole = 0;
- }
-#endif
-
- idx = 0x10;
- for (i = 0; i < node_nums; i++) {
- dram_base_mask_t d;
- resource_t basek, limitk, sizek; // 4 1T
-
- d = get_dram_base_mask(i);
-
- if (!(d.mask & 1)) continue;
- basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
- limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
-
- sizek = limitk - basek;
-
- /* see if we need a hole from 0xa0000 to 0xbffff */
- if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
- ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
- idx += 0x10;
- basek = (8*64)+(16*16);
- sizek = limitk - ((8*64)+(16*16));
-
- }
-
- /* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
- if (basek <= mmio_basek) {
- unsigned pre_sizek;
- pre_sizek = mmio_basek - basek;
- if (pre_sizek > 0) {
- ram_resource(dev, (idx | i), basek, pre_sizek);
- idx += 0x10;
- sizek -= pre_sizek;
- }
- basek = mmio_basek;
- }
- if ((basek + sizek) <= 4*1024*1024) {
- sizek = 0;
- }
- else {
- basek = 4*1024*1024;
- sizek -= (4*1024*1024 - mmio_basek);
- }
- }
-
- ram_resource(dev, (idx | i), basek, sizek);
- idx += 0x10;
- printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
- i, mmio_basek, basek, limitk);
- }
-
- add_uma_resource_below_tolm(dev, 7);
-
- for (link = dev->link_list; link; link = link->next) {
- if (link->children) {
- assign_resources(link);
- }
- }
-}
-
-/* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */
-static void f15_pci_domain_scan_bus(device_t dev)
-{
- struct bus *link = dev->link_list;
- pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff);
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = domain_read_resources,
- .set_resources = domain_set_resources,
- .init = DEVICE_NOOP,
- .scan_bus = f15_pci_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
-};
-
-static void sysconf_init(device_t dev) // first node
-{
- sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
- node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
-}
-
-static void add_more_links(device_t dev, unsigned total_links)
-{
- struct bus *link, *last = NULL;
- int link_num;
-
- for (link = dev->link_list; link; link = link->next)
- last = link;
-
- if (last) {
- int links = total_links - last->link_num;
- link_num = last->link_num;
- if (links > 0) {
- link = malloc(links*sizeof(*link));
- if (!link)
- die("Couldn't allocate more links!\n");
- memset(link, 0, links*sizeof(*link));
- last->next = link;
- }
- }
- else {
- link_num = -1;
- link = malloc(total_links*sizeof(*link));
- memset(link, 0, total_links*sizeof(*link));
- dev->link_list = link;
- }
-
- for (link_num = link_num + 1; link_num < total_links; link_num++) {
- link->link_num = link_num;
- link->dev = dev;
- link->next = link + 1;
- last = link;
- link = link->next;
- }
- last->next = NULL;
-}
-
-static void cpu_bus_scan(device_t dev)
-{
- struct bus *cpu_bus;
- device_t dev_mc;
-#if CONFIG_CBB
- device_t pci_domain;
-#endif
- int i,j;
- int coreid_bits;
- int core_max = 0;
- unsigned ApicIdCoreIdSize;
- unsigned core_nums;
- int siblings = 0;
- unsigned int family;
-
-#if CONFIG_CBB
- dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
- if (dev_mc && dev_mc->bus) {
- printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
- pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
- printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
- dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
- printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
- } else {
- printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
- }
- printk(BIOS_DEBUG, "\n");
- }
- dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
- if (!dev_mc) {
- dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
- if (dev_mc && dev_mc->bus) {
- printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
- pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
- if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
- printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
- dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
- printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
- while (dev_mc) {
- printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
- dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
- printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
- dev_mc = dev_mc->sibling;
- }
- }
- }
- }
- }
-#endif
- dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
- if (!dev_mc) {
- printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
- die("");
- }
- sysconf_init(dev_mc);
-#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
- if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe
- if (pci_domain->link_list && !pci_domain->link_list->next) {
- struct bus *new_link = new_link(pci_domain);
- pci_domain->link_list->next = new_link;
- new_link->link_num = 1;
- new_link->dev = pci_domain;
- new_link->children = 0;
- printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
- }
- pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
- }
-#endif
-
- /* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
- core_max = 1 << (coreid_bits & 0x000F); //mnc
-
- ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
- if (ApicIdCoreIdSize) {
- core_nums = (1 << ApicIdCoreIdSize) - 1;
- } else {
- core_nums = 3; //quad core
- }
-
- /* Find which cpus are present */
- cpu_bus = dev->link_list;
- for (i = 0; i < node_nums; i++) {
- device_t cdb_dev;
- unsigned busn, devn;
- struct bus *pbus;
-
- busn = CONFIG_CBB;
- devn = CONFIG_CDB + i;
- pbus = dev_mc->bus;
-#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
- if (i >= 32) {
- busn--;
- devn -= 32;
- pbus = pci_domain->link_list->next;
- }
-#endif
-
- /* Find the cpu's pci device */
- cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
- if (!cdb_dev) {
- /* If I am probing things in a weird order
- * ensure all of the cpu's pci devices are found.
- */
- int fn;
- for (fn = 0; fn <= 5; fn++) { //FBDIMM?
- cdb_dev = pci_probe_dev(NULL, pbus,
- PCI_DEVFN(devn, fn));
- }
- cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
- } else {
- /* Ok, We need to set the links for that device.
- * otherwise the device under it will not be scanned
- */
- add_more_links(cdb_dev, 8);
- }
-
- family = cpuid_eax(1);
- family = (family >> 20) & 0xFF;
- if (family == 1) { //f10
- u32 dword;
- cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
- dword = pci_read_config32(cdb_dev, 0xe8);
- siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
- } else if (family == 6) {//f15
- cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5));
- if (cdb_dev && cdb_dev->enabled) {
- siblings = pci_read_config32(cdb_dev, 0x84);
- siblings &= 0xFF;
- }
- } else {
- siblings = 0; //default one core
- }
- int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
- dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
-
- for (j = 0; j <= siblings; j++) {
- u32 lapicid_start = 0;
-
- /*
- * APIC ID calucation is tightly coupled with AGESA v5 code.
- * This calculation MUST match the assignment calculation done
- * in LocalApicInitializationAtEarly() function.
- * And reference GetLocalApicIdForCore()
- *
- * Apply apic enumeration rules
- * For systems with >= 16 APICs, put the IO-APICs at 0..n and
- * put the local-APICs at m..z
- *
- * This is needed because many IO-APIC devices only have 4 bits
- * for their APIC id and therefore must reside at 0..15
- */
-
- u8 plat_num_io_apics = 3; /* FIXME */
-
- if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
- lapicid_start = (plat_num_io_apics - 1) / core_max;
- lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
- }
-#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34)
- u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0);
-#else
- u32 apic_id = (i * core_max) + j + lapicid_start;
-#endif
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
- i, j, apic_id);
-
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
- if (cpu)
- amd_cpu_topology(cpu, i, j);
- } //j
- }
-}
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = cpu_bus_scan,
-};
-
-static void root_complex_enable_dev(struct device *dev)
-{
- static int done = 0;
-
- if (!done) {
- setup_bsp_ramtop();
- done = 1;
- }
-
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = {
- CHIP_NAME("AMD FAM15 Root Complex")
- .enable_dev = root_complex_enable_dev,
-};
diff --git a/src/northbridge/amd/agesa/family15/reset_test.h b/src/northbridge/amd/agesa/family15/reset_test.h
deleted file mode 100644
index 61de4d9895..0000000000
--- a/src/northbridge/amd/agesa/family15/reset_test.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * copy from src/northbridge/amd/amdfam10/reset_test.c
- */
-
-#ifndef _RESET_TEST_H_
-#define _RESET_TEST_H_
-
-#include <arch/io.h>
-#include "amdfam10.h" /* NODE_PCI */
-
-#define NODE_ID 0x60
-#define HT_INIT_CONTROL 0x6c
-#define HTIC_ColdR_Detect (1 << 4)
-#define HTIC_BIOSR_Detect (1 << 5)
-#define HTIC_INIT_Detect (1 << 6)
-
-static inline u32 warm_reset_detect(u8 nodeid)
-{
- u32 htic;
- pci_devfn_t device;
- device = NODE_PCI(nodeid, 0);
- htic = pci_io_read_config32(device, HT_INIT_CONTROL);
- return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
-}
-
-static inline void distinguish_cpu_resets(u8 nodeid)
-{
- u32 htic;
- pci_devfn_t device;
- device = NODE_PCI(nodeid, 0);
- htic = pci_io_read_config32(device, HT_INIT_CONTROL);
- htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
- pci_io_write_config32(device, HT_INIT_CONTROL, htic);
-}
-
-#endif
diff --git a/src/northbridge/amd/agesa/family15/state_machine.c b/src/northbridge/amd/agesa/family15/state_machine.c
deleted file mode 100644
index 83eadb0de0..0000000000
--- a/src/northbridge/amd/agesa/family15/state_machine.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "Porting.h"
-#include "AGESA.h"
-
-#include <cbmem.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
-{
-}
-
-void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
-{
-}
-
-void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
-{
-}
-
-void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
-{
- backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
-}
-
-void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
-{
- OemInitResume(&Resume->S3DataBlock);
-}
-
-void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
-{
-}
-
-void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
-{
- EmptyHeap();
-}
-
-void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
-{
-}
-
-void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
-{
- OemS3LateRestore(&S3Late->S3DataBlock);
-}
-
-void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
-{
-}
-
-void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
-{
-}
-
-void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
-{
-}
-
-void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
-{
- OemS3Save(&S3Save->S3DataBlock);
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 22:07:14 +0000