diff options
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 6 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 4 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 96321637b3..516f0fc6ae 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -402,7 +402,7 @@ static void disable_probes(void) print_debug("Disabling read/write/fill probes for UP... "); val=pci_read_config32(NODE_HT(0), 0x68); - val |= 0x0000040f; + val |= (1<<10)|(1<<9)|(1<<8)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1 << 0); pci_write_config32(NODE_HT(0), 0x68, val); print_debug("done.\r\n"); @@ -475,7 +475,6 @@ static bool check_connection(u8 src, u8 dest, u8 link) { /* this function does 2 things: * 1) detect whether the coherent HT link is connected. - * After this step follows a small idle loop. * 2) verify that the coherent hypertransport link * is established and actually working by reading the * remote node's vendor/device id @@ -492,9 +491,6 @@ static bool check_connection(u8 src, u8 dest, u8 link) if ( (val&0x17) != 0x03) return 0; - /* idle loop to make sure the link is established */ - for (val=0;val<16;val++); - /* 2) */ val=pci_read_config32(NODE_HT(dest),0); if(val != 0x11001022) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 1c1e475f2c..fac6e1adee 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -315,7 +315,7 @@ static void setup_default_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -350,7 +350,7 @@ static void setup_default_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 |