4 files changed, 17 insertions, 33 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 321e87d7d0..96938b2c63 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -922,13 +922,11 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 
 #include "nums.h"
 
-#ifdef __PRE_RAM__
 #if NODE_NUMS == 64
 	 #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
 	 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
-#endif
 
 /* Include wrapper for MCT (works for DDR2 or DDR3) */
 #include <northbridge/amd/amdmct/wrappers/mcti.h>
@@ -989,11 +987,8 @@ struct sys_info {
 	struct DCTStatStruc DCTstatA[NODE_NUMS];
 } __packed;
 
-#ifndef __PRE_RAM__
 struct device *get_node_pci(u32 nodeid, u32 fn);
-#endif
 
-#ifdef __PRE_RAM__
 void showallroutes(int level, pci_devfn_t dev);
 
 void setup_resource_map_offset(const u32 *register_values, u32 max, u32
@@ -1017,8 +1012,6 @@ u32 get_sblk(void);
 u8 get_sbbusn(u8 sblk);
 void set_bios_reset(void);
 
-#endif
-
 #include "northbridge/amd/amdht/porting.h"
 BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
 
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index 292049eff9..3e8c2fbeac 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -14,15 +14,14 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
-
 #include <arch/cpu.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
 #include "raminit.h"
 #include <northbridge/amd/amdmct/amddefs.h>
 
-#ifndef __PRE_RAM__
-#include <include/device/pci_ops.h>
-#include <include/device/pci_def.h>
+#ifndef __SIMPLE_DEVICE__
 u32 Get_NB32(u32 dev, u32 reg)
 {
 	return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg);
diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c
index 39c2bfb4b2..ed5556ff70 100644
--- a/src/northbridge/amd/amdfam10/util.c
+++ b/src/northbridge/amd/amdfam10/util.c
@@ -21,11 +21,10 @@
  * It can be called after RAM is set up by including amdfam10.h and enabling the
  * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc.
  */
-#ifndef __PRE_RAM__
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#endif
+
 #include "amdfam10.h"
 
 /* Function 1 */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 1517398a33..1fdbc169e4 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -79,7 +79,7 @@ static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct,
 {
 	if (is_fam15h()) {
 		uint32_t dword;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
 		pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
 		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -108,7 +108,7 @@ static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct,
 {
 	if (is_fam15h()) {
 		uint32_t dword;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
 		pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
 		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -158,7 +158,7 @@ static uint32_t read_amd_dct_index_register_dct(struct device *dev,
 {
 	if (is_fam15h()) {
 		uint32_t dword;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
 		pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1);
 #else
 		struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1);
@@ -253,7 +253,6 @@ static struct amd_s3_persistent_data *map_s3nv_in_nvram(void)
 	return persistent_data;
 }
 
-#ifdef __PRE_RAM__
 int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
 {
 	struct amd_s3_persistent_data *persistent_data;
@@ -269,14 +268,20 @@ int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatS
 
 	return 0;
 }
-#endif
 
-#ifdef __RAMSTAGE__
 static uint64_t rdmsr_uint64_t(unsigned long index) {
 	msr_t msr = rdmsr(index);
 	return (((uint64_t)msr.hi) << 32) | ((uint64_t)msr.lo);
 }
 
+static void wrmsr_uint64_t(unsigned long index, uint64_t value)
+{
+	msr_t msr;
+	msr.hi = (value & 0xffffffff00000000ULL) >> 32;
+	msr.lo = (value & 0xffffffff);
+	wrmsr(index, msr);
+}
+
 static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node,
 					   uint8_t dct, uint8_t nb_pstate,
 					   uint32_t reg)
@@ -557,7 +562,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da
 		}
 	}
 }
-#else
+
 static void write_config32_dct_nbpstate(pci_devfn_t dev, uint8_t node,
 					uint8_t dct, uint8_t nb_pstate,
 					uint32_t reg, uint32_t value)
@@ -615,15 +620,6 @@ static void write_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node,
 
 	return write_amd_dct_index_register(dev, index_ctl_reg, index, value);
 }
-#endif
-
-#ifdef __PRE_RAM__
-static void wrmsr_uint64_t(unsigned long index, uint64_t value) {
-	msr_t msr;
-	msr.hi = (value & 0xffffffff00000000ULL) >> 32;
-	msr.lo = (value & 0xffffffff);
-	wrmsr(index, msr);
-}
 
 void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only)
 {
@@ -1130,9 +1126,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
 		}
 	}
 }
-#endif
 
-#ifdef __RAMSTAGE__
 int8_t save_mct_information_to_nvram(void)
 {
 	uint8_t nvram;
@@ -1206,7 +1200,6 @@ int8_t save_mct_information_to_nvram(void)
 
 	return 0;
 }
-#endif
 
 int8_t restore_mct_information_from_nvram(uint8_t training_only)
 {