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-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c2
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c5
2 files changed, 6 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 693500e40c..cec708c2b1 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3400,6 +3400,8 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
u8 max_dimms;
// FIXME: skip for Ax
+
+ dev = pDCTstat->dev_dct;
/* Tri-state unused ODTs when motherboard termination is available */
max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 93f000de4c..7e111917d1 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -197,13 +197,16 @@ u16 mctGet_NVbits(u8 index)
case NV_CS_SpareCTL:
val = 0; /* Disabled */
//val = 1; /* Enabled */
+ break;
case NV_SyncOnUnEccEn:
val = 0; /* Disabled */
//val = 1; /* Enabled */
+ break;
case NV_Unganged:
/* channel interleave is better performance than ganged mode at this time */
val = 1; /* Enabled */
//val = 0; /* Disabled */
+ break;
case NV_ChannelIntlv:
val = 5; /* Not currently checked in mctchi_d.c */
/* Bit 0 = 0 - Disable
@@ -213,7 +216,7 @@ u16 mctGet_NVbits(u8 index)
* 10b - Hash*, XOR of address bits [20:16, 6]
* 11b - Hash*, XOR of address bits [20:16, 9]
*/
-
+ break;
}
return val;