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-rw-r--r--src/northbridge/amd/amdk8/get_sblk_pci1234.c11
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c23
2 files changed, 33 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index d52a7f761a..eff6ca1c62 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -78,9 +78,12 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
extern unsigned pci1234[];
+extern unsigned hcdn[];
extern unsigned hc_possible_num;
extern unsigned sblk;
+unsigned hcdn_reg[4]; // defined in northbridge.c
+
/* why we need pci1234 array
final result for pci1234 will be
pci1234[0] will record sblink and bus range
@@ -176,6 +179,10 @@ void get_sblk_pci1234(void)
set the node_id and link_id that could have ht chain in the one array,
then check if is enabled.... then update final value
*/
+ //here we need to set hcdn
+ //1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
+ //2. so at the same time we need update hsdn with hcdn_reg here
+
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(j=0;j<4;j++) {
uint32_t dwordx;
@@ -183,6 +190,7 @@ void get_sblk_pci1234(void)
dwordx &=0xffff0ff1; //keep bus num, node_id, link_num, enable bits
if((dwordx & 0xff1) == dword) { //SBLINK
pci1234[0] = dwordx;
+ hcdn[0] = hcdn_reg[j];
continue;
}
if((dwordx & 1) == 1) {
@@ -191,6 +199,7 @@ void get_sblk_pci1234(void)
for(i=1;i<hc_possible_num;i++) {
if((dwordx & 0xff0) == (pci1234[i] & 0xff0)) {
pci1234[i] = dwordx;
+ hcdn[i] = hcdn_reg[j];
break;
}
}
@@ -198,6 +207,7 @@ void get_sblk_pci1234(void)
for(i=1;i<hc_possible_num;i++) {
if((dwordx & 0xff0) == (dwordx & pci1234[i] & 0xff0)) {
pci1234[i] = dwordx;
+ hcdn[i] = hcdn_reg[j];
break;
}
}
@@ -207,6 +217,7 @@ void get_sblk_pci1234(void)
for(i=1;i<hc_possible_num;i++) {
if((pci1234[i] & 1) != 1) {
pci1234[i] = 0;
+ hcdn[i] = 0x20202020;
}
}
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index d2db902beb..d7d2f2daf1 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -97,6 +97,8 @@ static unsigned int amdk8_nodeid(device_t dev)
return (dev->path.u.pci.devfn >> 3) - 0x18;
}
+unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234
+
static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
{
#if 0
@@ -107,8 +109,11 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
uint32_t link_type;
+ int i;
uint32_t busses, config_busses;
unsigned free_reg, config_reg;
+ unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
+
dev->link[link].cap = 0x80 + (link *0x20);
do {
link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
@@ -195,7 +200,10 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
/* Now we can scan all of the subordinate busses i.e. the
* chain on the hypertranport link
*/
- max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max, offset_unitid);
+ for(i=0;i<4;i++) {
+ ht_unitid_base[i] = 0x20;
+ }
+ max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max, ht_unitid_base, offset_unitid);
#if 0
printk_debug("%s Hyper transport scan link: %d new max: %d\n",
@@ -214,6 +222,19 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin
(dev->link[link].subordinate << 24);
f1_write_config32(config_reg, config_busses);
+ {
+ // config config_reg, and ht_unitid_base to update hcdn_reg;
+ int index;
+ unsigned temp = 0;
+ index = (config_reg-0xe0) >> 2;
+ for(i=0;i<4;i++) {
+ temp |= (ht_unitid_base[i] & 0xff) << (i*8);
+ }
+
+ hcdn_reg[index] = temp;
+
+ }
+
#if 0
printk_debug("%s Hypertransport scan link: %d done\n",
dev_path(dev), link);