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-rw-r--r--src/northbridge/amd/amdfam10/Config.lb2
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c23
-rw-r--r--src/northbridge/amd/gx1/Config.lb2
-rw-r--r--src/northbridge/amd/gx1/northbridge.c12
-rw-r--r--src/northbridge/amd/gx2/Config.lb2
-rw-r--r--src/northbridge/amd/gx2/northbridge.c14
-rw-r--r--src/northbridge/amd/lx/Config.lb2
-rw-r--r--src/northbridge/amd/lx/northbridge.c15
8 files changed, 70 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb
index 5e9081991d..79b7b49280 100644
--- a/src/northbridge/amd/amdfam10/Config.lb
+++ b/src/northbridge/amd/amdfam10/Config.lb
@@ -19,8 +19,10 @@
uses AGP_APERTURE_SIZE
uses HAVE_ACPI_TABLES
+uses HAVE_HIGH_TABLES
default AGP_APERTURE_SIZE=0x4000000
+default HAVE_HIGH_TABLES=1
config chip.h
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 92f9ea3819..6a9504ccc1 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -911,6 +911,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int i)
#endif
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM == 1
@@ -1084,6 +1089,15 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
+#if HAVE_HIGH_TABLES==1
+ if (i==0 && high_tables_base==0) {
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+ printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+ high_tables_base);
+ }
+#endif
}
#if CONFIG_AMDMCT == 0
#if HW_MEM_HOLE_SIZEK != 0
@@ -1108,6 +1122,15 @@ static void pci_domain_set_resources(device_t dev)
}
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
+#if HAVE_HIGH_TABLES==1
+ printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+ i, mmio_basek, basek, limitk);
+ if (i==0 && high_tables_base==0) {
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+ }
+#endif
}
for(link = 0; link < dev->links; link++) {
diff --git a/src/northbridge/amd/gx1/Config.lb b/src/northbridge/amd/gx1/Config.lb
index 16463e0ccd..adb96c3c64 100644
--- a/src/northbridge/amd/gx1/Config.lb
+++ b/src/northbridge/amd/gx1/Config.lb
@@ -1,2 +1,4 @@
+uses HAVE_HIGH_TABLES
config chip.h
driver northbridge.o
+default HAVE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 247c24304e..63cc003df0 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -126,6 +126,11 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
@@ -168,6 +173,13 @@ static void pci_domain_set_resources(device_t dev)
*/
tolmk = tomk;
}
+
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
+
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, tolmk);
diff --git a/src/northbridge/amd/gx2/Config.lb b/src/northbridge/amd/gx2/Config.lb
index 4b361f5c90..342dac967c 100644
--- a/src/northbridge/amd/gx2/Config.lb
+++ b/src/northbridge/amd/gx2/Config.lb
@@ -1,5 +1,7 @@
+uses HAVE_HIGH_TABLES
config chip.h
driver northbridge.o
object northbridgeinit.o
object chipsetinit.o
object grphinit.o
+default HAVE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index e285e52cb6..bfcef1af47 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -501,6 +501,11 @@ static struct device_operations cpu_bus_ops = {
void chipsetInit (void);
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void enable_dev(struct device *dev)
{
printk_debug("gx2 north: enable_dev\n");
@@ -512,6 +517,7 @@ static void enable_dev(struct device *dev)
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
extern void cpubug(void);
+ u32 tomk;
printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
northbridgeinit();
@@ -524,7 +530,13 @@ static void enable_dev(struct device *dev)
graphics_init();
dev->ops = &pci_domain_ops;
pci_set_method(dev);
- ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE);
+ tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE;
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
+ ram_resource(dev, 0, 0, tomk);
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/amd/lx/Config.lb b/src/northbridge/amd/lx/Config.lb
index 9b1d4c2c71..b9388893ab 100644
--- a/src/northbridge/amd/lx/Config.lb
+++ b/src/northbridge/amd/lx/Config.lb
@@ -1,4 +1,6 @@
+uses HAVE_HIGH_TABLES
config chip.h
driver northbridge.o
object northbridgeinit.o
object grphinit.o
+default HAVE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 9762510cf4..390c94cf78 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -415,19 +415,32 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
int idx;
+ u32 tomk;
device_t mc_dev;
printk_spew(">> Entering northbridge.c: %s\n", __func__);
mc_dev = dev->link[0].children;
if (mc_dev) {
+ tomk = get_systop() / 1024;
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); // Systop - 1 MB -> KB
+ ram_resource(dev, idx++, 1024, tomk - 1024); // Systop - 1 MB -> KB
+
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
assign_resources(&dev->link[0]);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-20 00:11:34 +0000