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-rw-r--r--src/northbridge/amd/agesa/family10/northbridge.c14
-rw-r--r--src/northbridge/amd/agesa/family12/amdfam12_conf.c4
-rw-r--r--src/northbridge/amd/agesa/family14/amdfam14_conf.c4
-rw-r--r--src/northbridge/amd/amdfam10/early_ht.c2
-rw-r--r--src/northbridge/amd/amdfam10/ht_config.c10
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c4
-rw-r--r--src/northbridge/amd/amdfam10/reset_test.c4
-rw-r--r--src/northbridge/amd/amdht/h3finit.c4
-rw-r--r--src/northbridge/amd/amdht/ht_wrapper.c2
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c2
-rw-r--r--src/northbridge/amd/amdk8/incoherent_ht.c4
-rw-r--r--src/northbridge/amd/amdk8/raminit_f.c2
-rw-r--r--src/northbridge/amd/amdk8/raminit_f_dqs.c2
-rw-r--r--src/northbridge/amd/amdk8/reset_test.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mport_d.c4
-rw-r--r--src/northbridge/amd/lx/northbridge.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c4
-rw-r--r--src/northbridge/amd/pi/00630F01/northbridge.c4
-rw-r--r--src/northbridge/amd/pi/00660F01/northbridge.c4
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c4
22 files changed, 45 insertions, 45 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index ec17b13b33..2c9f3aae28 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -102,7 +102,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 256; index++) {
if ((sysconf.conf_io_addrx[index+4] == 0)) {
- sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
+ sysconf.conf_io_addr[index+4] = (nodeid & 0x3f);
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
return index;
}
@@ -118,7 +118,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 64; index++) {
if (sysconf.conf_mmio_addrx[index+8] == 0) {
- sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+ sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f);
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
return index;
}
@@ -136,7 +136,7 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
val = (nodeid & 0x3f); // 6 bits used
sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
- val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+ val = 3 | ((linkn & 0x7)<<4); // 8 bits used
sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit
if (sysconf.io_addr_num<(index+1))
@@ -150,9 +150,9 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
/* io range allocation */
index = (reg-0x80)>>3;
- val = (nodeid & 0x3f) ; // 6 bits used
+ val = (nodeid & 0x3f); // 6 bits used
sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
- val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+ val = 3 | ((linkn & 0x7)<<4); // 8 bits used
sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
if (sysconf.mmio_addr_num<(index+1))
@@ -478,7 +478,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource,
store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8);
}
else if (resource->flags & IORESOURCE_MEM) {
- set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
+ set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8]
store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);
}
resource->flags |= IORESOURCE_STORED;
@@ -759,7 +759,7 @@ static void amdfam10_domain_set_resources(device_t dev)
if (!(d.mask & 1)) continue;
basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
- limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
+ limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
sizek = limitk - basek;
/* see if we need a hole from 0xa0000 to 0xbffff */
diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
index 3c91d2d97d..64d904f8e8 100644
--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c
+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
@@ -89,7 +89,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 256; index++) {
if (sysconf.conf_io_addrx[index+4] == 0) {
- sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
+ sysconf.conf_io_addr[index+4] = (nodeid & 0x3f);
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
return index;
}
@@ -105,7 +105,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 64; index++) {
if (sysconf.conf_mmio_addrx[index+8] == 0) {
- sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+ sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f);
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
return index;
}
diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
index 28c16fb992..dda6bf96cb 100644
--- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c
+++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
@@ -89,7 +89,7 @@ static u32 get_io_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 256; index++) {
if (sysconf.conf_io_addrx[index+4] == 0) {
- sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
+ sysconf.conf_io_addr[index+4] = (nodeid & 0x3f);
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
return index;
}
@@ -105,7 +105,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 64; index++) {
if (sysconf.conf_mmio_addrx[index+8] == 0) {
- sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+ sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f);
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
return index;
}
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 812935e108..36814638a9 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -106,7 +106,7 @@ static void enumerate_ht_chain(void)
}
real_last_unitid = next_unitid;
real_last_pos = pos;
- ht_dev_num++ ;
+ ht_dev_num++;
#endif
#if !CONFIG_HT_CHAIN_END_UNITID_BASE
if (!next_unitid)
diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c
index 226d9a8c0a..9259147625 100644
--- a/src/northbridge/amd/amdfam10/ht_config.c
+++ b/src/northbridge/amd/amdfam10/ht_config.c
@@ -129,7 +129,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 256; index++) {
if (sysconf.conf_io_addrx[index+4] == 0) {
- sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
+ sysconf.conf_io_addr[index+4] = (nodeid & 0x3f);
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
return index;
}
@@ -144,7 +144,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
for (index = 0; index < 64; index++) {
if (sysconf.conf_mmio_addrx[index+8] == 0) {
- sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
+ sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f);
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
return index;
}
@@ -164,7 +164,7 @@ void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
val = (nodeid & 0x3f); // 6 bits used
sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
- val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+ val = 3 | ((linkn & 0x7)<<4); // 8 bits used
sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit
if (sysconf.io_addr_num < (index+1))
@@ -180,9 +180,9 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
/* io range allocation */
index = (reg-0x80)>>3;
- val = (nodeid & 0x3f) ; // 6 bits used
+ val = (nodeid & 0x3f); // 6 bits used
sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
- val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
+ val = 3 | ((linkn & 0x7)<<4); // 8 bits used
sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
if (sysconf.mmio_addr_num<(index+1))
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 354e70316f..40f57046e8 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -577,7 +577,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource,
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8);
} else if (resource->flags & IORESOURCE_MEM) {
- set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
+ set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8]
store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);
}
resource->flags |= IORESOURCE_STORED;
@@ -966,7 +966,7 @@ static void amdfam10_domain_set_resources(device_t dev)
if (!(d.mask & 1)) continue;
basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
- limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
+ limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
sizek = limitk - basek;
/* see if we need a hole from 0xa0000 to 0xbffff */
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 7ddf93f120..0e64397ff0 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -108,7 +108,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
u32 val;
// put node and link in correct bit
- val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8) ;
+ val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8);
for (reg = 0xE0; reg < 0xF0; reg += 0x04) {
u32 config_map;
@@ -131,7 +131,7 @@ u32 get_sblk(void)
u32 reg;
/* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64);
- return ((reg>>8) & 3) ;
+ return ((reg>>8) & 3);
}
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index b4838b44d5..2baf886c31 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1541,7 +1541,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat)
pDat->PortList[i+1].CompositeFrequencyCap = temp;
ASSERT (temp != 0);
- for (j = 19; ; j--)
+ for (j = 19;; j--)
{
if ((j == 16) || (j == 15))
continue;
@@ -1691,7 +1691,7 @@ static void hammerSublinkFixup(sMainData *pDat)
pDat->PortList[hiIndex].CompositeFrequencyCap = temp;
pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp;
- for (k = 19; ; k--)
+ for (k = 19;; k--)
{
if ((j == 16) || (j == 15))
continue;
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 169b4b3369..4c68f41337 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -73,7 +73,7 @@ static u32 get_nodes(void)
u32 nodes;
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0);
- nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ;
+ nodes = ((pci_read_config32(dev, 0x60)>>4) & 7);
#if CONFIG_MAX_PHYSICAL_CPUS > 8
nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
#endif
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 887a23b1f0..ef4b829397 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -1572,7 +1572,7 @@ static unsigned verify_dualcore(unsigned nodes)
totalcpus = 0;
for (node = 0; node < nodes; node++) {
- tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
+ tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3;
totalcpus += (tmp + 1);
}
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 9fa0034848..48a4709f74 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -435,7 +435,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
out:
#endif
-end_of_chain: ;
+end_of_chain:;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
@@ -663,7 +663,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4;
busn = (reg & 0xff0000)>>16;
- dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ;
+ dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos);
dword &= ~(0xffff<<8);
dword |= (reg & 0xffff0000)>>8;
pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword);
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 4ef621c96d..a42614e3cd 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1607,7 +1607,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
{
const struct mem_param *param;
- for (param = &speed[0]; param->cycle_time ; param++) {
+ for (param = &speed[0]; param->cycle_time; param++) {
if (min_cycle_time > (param+1)->cycle_time) {
break;
}
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 2d05951513..0cea94a0a2 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -479,7 +479,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
uint8_t *buf_a, *buf_b;
uint32_t ecc_bit;
uint32_t dword;
- uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8
+ uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8]; //8 node, channel 2, receiver 8
int i;
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index cfc5dda718..53f24339a3 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -77,7 +77,7 @@ static inline unsigned get_sblk(void)
u32 reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
- return ((reg>>8) & 3) ;
+ return ((reg>>8) & 3);
}
static inline unsigned get_sbbusn(unsigned sblk)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 87863b143e..d3ae2a3cf4 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -1700,7 +1700,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
if (!(pDCTstat->DIMMValid & (1 << val)))
/*disable memclk*/
DramTimingLo |= 1 << (dword+24);
- dword++ ;
+ dword++;
}
}
}
@@ -3629,7 +3629,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
p = (u8 *) pDCTstat;
start = 0;
stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
- for (i = start; i < stop ; i++) {
+ for (i = start; i < stop; i++) {
p[i] = 0;
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index da2a4fe0c6..bd26a6fc45 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -226,7 +226,7 @@ static const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2};
CS3 M[B,A]_CLK_H/L[5]
Then:
- ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7
+ ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7
MEMCLK_MAPPING EQU 00010000b, 00000100b, 00001000b, 00100000b, 00000000b, 00000000b, 00000000b, 00000000b
*/
@@ -5258,7 +5258,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
val = p[dword];
byte &= ~val;
}
- dword++ ;
+ dword++;
}
DramTimingLo &= ~(0xff << 24);
DramTimingLo |= byte << 24;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c
index 5030562c7c..3c15e3f845 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c
@@ -16,7 +16,7 @@
static void AmdMemPCIRead(SBDFO loc, u32 *Value)
{
/* Convert SBDFO into a CF8 Address */
- loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ;
+ loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16);
loc |= 0x80000000;
outl(loc, 0xCF8);
@@ -27,7 +27,7 @@ static void AmdMemPCIRead(SBDFO loc, u32 *Value)
static void AmdMemPCIWrite(SBDFO loc, u32 *Value)
{
/* Convert SBDFO into a CF8 Address */
- loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ;
+ loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16);
loc |= 0x80000000;
outl(loc, 0xCF8);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index a40a628187..4b6090f1e5 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -402,7 +402,7 @@ static void pci_domain_enable(device_t dev)
// print_conf();
- do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
+ do_vsmbios(); // do the magic stuff here, so prepare your tambourine;)
// print_conf();
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 395d9253a9..3be0248571 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -672,8 +672,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */
/* Wait 2 PORT61 ticks. between 15us and 30us */
/* This would be endless if the timer is stuck. */
- while ((inb(0x61))) ; /* find the first edge */
- while (!(~inb(0x61))) ;
+ while ((inb(0x61))); /* find the first edge */
+ while (!(~inb(0x61)));
/* Force Precharge All on the next command, auto-refresh */
msrnum = MC_CFCLK_DBUG;
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 6769d111b0..fb115ff7b2 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -377,7 +377,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
}
else if (resource->flags & IORESOURCE_MEM) {
- set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8]
+ set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8]
}
resource->flags |= IORESOURCE_STORED;
snprintf(buf, sizeof(buf), " <node %x link %x>",
@@ -795,7 +795,7 @@ static void domain_set_resources(device_t dev)
if (!(d.mask & 1)) continue;
basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
- limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ;
+ limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
sizek = limitk - basek;
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 1ca0df98e4..c44641965a 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -370,7 +370,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
}
else if (resource->flags & IORESOURCE_MEM) {
- set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8]
+ set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8]
}
resource->flags |= IORESOURCE_STORED;
snprintf(buf, sizeof(buf), " <node %x link %x>",
@@ -802,7 +802,7 @@ static void domain_set_resources(device_t dev)
if (!(d.mask & 1))
continue;
basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
- limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ;
+ limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
sizek = limitk - basek;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 334cdb215c..c87d68abb7 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -391,7 +391,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
}
else if (resource->flags & IORESOURCE_MEM) {
- set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8]
+ set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8]
}
resource->flags |= IORESOURCE_STORED;
snprintf(buf, sizeof(buf), " <node %x link %x>",
@@ -824,7 +824,7 @@ static void domain_set_resources(device_t dev)
if (!(d.mask & 1)) continue;
basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
- limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ;
+ limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
sizek = limitk - basek;
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 18:00:45 +0000