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-rw-r--r--src/northbridge/amd/pi/00630F01/acpi/northbridge.asl4
-rw-r--r--src/northbridge/amd/pi/00630F01/dimmSpd.c4
-rw-r--r--src/northbridge/amd/pi/00630F01/northbridge.c36
-rw-r--r--src/northbridge/amd/pi/00660F01/acpi/northbridge.asl16
-rw-r--r--src/northbridge/amd/pi/00660F01/northbridge.c23
-rw-r--r--src/northbridge/amd/pi/00730F01/acpi/northbridge.asl10
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c35
7 files changed, 63 insertions, 65 deletions
diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
index 689203a9e4..c2b3aac4c5 100644
--- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
@@ -50,7 +50,7 @@ Device(PBR2) {
Name(_ADR, 0x00020000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
+ If(PMOD) { Return(APS2) } /* APIC mode */
Return (PS2) /* PIC Mode */
} /* end _PRT */
} /* end PBR2 */
@@ -60,7 +60,7 @@ Device(PBR3) {
Name(_ADR, 0x00030000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS3) } /* APIC mode */
+ If(PMOD) { Return(APS3) } /* APIC mode */
Return (PS3) /* PIC Mode */
} /* end _PRT */
} /* end PBR3 */
diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c
index 889db62a4d..50eee51864 100644
--- a/src/northbridge/amd/pi/00630F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c
@@ -35,9 +35,9 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
if ((dev == 0) || (config == 0))
return AGESA_ERROR;
- if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
+ if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
return AGESA_ERROR;
- if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
+ if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
return AGESA_ERROR;
if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0]))
return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 0f9e5f5366..8a40280938 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -88,10 +88,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
- for (i=0; i<node_nums; i++)
+ tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -101,10 +101,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for (i=0; i<nodes; i++)
+ for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -131,7 +131,7 @@ static void get_fx_devs(void)
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
}
- printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
@@ -160,7 +160,7 @@ static u32 amdfam15_nodeid(device_t dev)
unsigned busn;
busn = dev->bus->secondary;
- if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)){
+ if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
@@ -403,8 +403,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate ))
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate))
break;
}
else
@@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev)
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
device_t reg_dev;
- if (reg<0xc0) { // mmio
+ if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30);
@@ -687,7 +687,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
*/
if (mem_hole.node_id == -1) {
resource_t limitk_pri = 0;
- for (i=0; i<node_nums; i++) {
+ for (i = 0; i < node_nums; i++) {
dram_base_mask_t d;
resource_t base_k, limit_k;
d = get_dram_base_mask(i);
@@ -811,11 +811,11 @@ static void domain_set_resources(device_t dev)
//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
/* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -981,7 +981,7 @@ static void cpu_bus_scan(device_t dev)
}
sysconf_init(dev_mc);
#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
- if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
+ if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe
if (pci_domain->link_list && !pci_domain->link_list->next) {
struct bus *new_link = new_link(pci_domain);
pci_domain->link_list->next = new_link;
@@ -1059,10 +1059,10 @@ static void cpu_bus_scan(device_t dev)
siblings = 0; //default one core
}
int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
- for (j = 0; j <= siblings; j++ ) {
+ for (j = 0; j <= siblings; j++) {
u32 lapicid_start = 0;
/*
@@ -1081,10 +1081,10 @@ static void cpu_bus_scan(device_t dev)
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start);
+ printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
index cde5182123..022b347d29 100644
--- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
@@ -50,7 +50,7 @@ Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
+ If(PMOD) { Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
@@ -60,7 +60,7 @@ Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
+ If(PMOD) { Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
@@ -70,7 +70,7 @@ Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
+ If(PMOD) { Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
@@ -80,7 +80,7 @@ Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
+ If(PMOD) { Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
@@ -90,7 +90,7 @@ Device(PBR8) {
Name(_ADR, 0x00020005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS8) } /* APIC mode */
+ If(PMOD) { Return(APS8) } /* APIC mode */
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
@@ -105,7 +105,7 @@ Device(PBRA) {
Name(_ADR, 0x00030003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSA) } /* APIC mode */
+ If(PMOD) { Return(APSA) } /* APIC mode */
Return (PSA) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
@@ -115,7 +115,7 @@ Device(PBRB) {
Name(_ADR, 0x00030004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSB) } /* APIC mode */
+ If(PMOD) { Return(APSB) } /* APIC mode */
Return (PSB) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
@@ -125,7 +125,7 @@ Device(PBRC) {
Name(_ADR, 0x00030005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSC) } /* APIC mode */
+ If(PMOD) { Return(APSC) } /* APIC mode */
Return (PSC) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index efee0a4f05..1ca0df98e4 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -100,10 +100,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for (i=0; i<nodes; i++)
+ for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -134,7 +134,7 @@ static void get_fx_devs(void)
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
}
- printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
@@ -396,9 +396,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate )
- )
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate))
#endif
break;
}
@@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev)
}
/* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -1059,10 +1058,10 @@ static void cpu_bus_scan(device_t dev)
siblings = 0;
}
int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
- for (j = 0; j <= siblings; j++ ) {
+ for (j = 0; j <= siblings; j++) {
u32 lapicid_start = 0;
/*
@@ -1081,10 +1080,10 @@ static void cpu_bus_scan(device_t dev)
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
+ printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
index 4e6d13e74e..f74b31a080 100644
--- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
@@ -50,7 +50,7 @@ Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
+ If(PMOD) { Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
@@ -60,7 +60,7 @@ Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
+ If(PMOD) { Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
@@ -70,7 +70,7 @@ Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
+ If(PMOD) { Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
@@ -80,7 +80,7 @@ Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
+ If(PMOD) { Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
@@ -90,7 +90,7 @@ Device(PBR8) {
Name(_ADR, 0x00020005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS8) } /* APIC mode */
+ If(PMOD) { Return(APS8) } /* APIC mode */
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 6d5418a532..b778da5903 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -83,9 +83,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+ tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
#if 0
// FIXME: can we use VGA reg instead?
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
@@ -97,7 +97,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
tempreg |= PCI_IO_BASE_NO_ISA;
}
#endif
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -107,10 +107,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for (i=0; i<nodes; i++)
+ for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -141,7 +141,7 @@ static void get_fx_devs(void)
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
}
- printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
@@ -417,9 +417,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate )
- )
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate))
#endif
break;
}
@@ -646,7 +645,7 @@ static void domain_read_resources(device_t dev)
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
device_t reg_dev;
- if (reg<0xc0) { // mmio
+ if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30);
@@ -709,7 +708,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
*/
if (mem_hole.node_id == -1) {
resource_t limitk_pri = 0;
- for (i=0; i<node_nums; i++) {
+ for (i = 0; i < node_nums; i++) {
dram_base_mask_t d;
resource_t base_k, limit_k;
d = get_dram_base_mask(i);
@@ -841,11 +840,11 @@ static void domain_set_resources(device_t dev)
//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
/* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -1011,7 +1010,7 @@ static void cpu_bus_scan(device_t dev)
}
sysconf_init(dev_mc);
#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
- if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
+ if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe
if (pci_domain->link_list && !pci_domain->link_list->next) {
struct bus *new_link = new_link(pci_domain);
pci_domain->link_list->next = new_link;
@@ -1090,10 +1089,10 @@ static void cpu_bus_scan(device_t dev)
siblings = 0; //default one core
}
int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
- for (j = 0; j <= siblings; j++ ) {
+ for (j = 0; j <= siblings; j++) {
u32 lapicid_start = 0;
/*
@@ -1112,10 +1111,10 @@ static void cpu_bus_scan(device_t dev)
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
+ printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 05:03:11 +0000