diff options
Diffstat (limited to 'src/northbridge/amd/lx')
| -rw-r--r-- | src/northbridge/amd/lx/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/grphinit.c | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/raminit.c | 14 |
4 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index 57a485eedc..09eba0791a 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_LX bool select HAVE_HIGH_TABLES select GEODE_VSA - + config VIDEO_MB int default 8 diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c index 85e6a45ba0..b245eea062 100644 --- a/src/northbridge/amd/lx/grphinit.c +++ b/src/northbridge/amd/lx/grphinit.c @@ -35,7 +35,7 @@ struct msrinit { }; static const struct msrinit geodelx_vga_msr[] = { - /* Enable the GLIU Memory routing to the hardware + /* Enable the GLIU Memory routing to the hardware * PDID1 : Port 4, GLIU0 * PBASE : 0x000A0 * PMASK : 0xFFFE0 @@ -71,9 +71,9 @@ void graphics_init(void) /* SoftVG initialization */ printk(BIOS_DEBUG, "Graphics init...\n"); - + geodelx_vga_msr_init(); - + /* Call SoftVG with the main configuration parameters. */ /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ @@ -94,7 +94,7 @@ void graphics_init(void) * so we can add the real value in megabytes */ - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK); vrWrite(wClassIndex, wData); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4dd29d134f..6eba99d9df 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -262,7 +262,7 @@ void print_conf(void) #endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } -/* todo: add a resource record. We don't do this here because this may be called when +/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. */ int sizeram(void) diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 75d77f0305..9014fb1de3 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,9 +22,9 @@ #include <spd.h> #include "southbridge/amd/cs5536/cs5536.h" -static const unsigned char NumColAddr[] = { - 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F +static const unsigned char NumColAddr[] = { + 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; static void banner(const char *s) @@ -35,8 +35,8 @@ static void banner(const char *s) static void hcf(void) { print_emerg("DIE\n"); - /* this guarantees we flush the UART fifos (if any) and also - * ensures that things, in general, keep going so no debug output + /* this guarantees we flush the UART fifos (if any) and also + * ensures that things, in general, keep going so no debug output * is lost */ while (1) @@ -231,7 +231,7 @@ static void set_refresh_rate(void) } msr = rdmsr(MC_CF07_DATA); - msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) + msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16) << CF07_LOWER_REF_INT_SHIFT; wrmsr(MC_CF07_DATA, msr); } @@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* If both Page Size = "Not Installed" we have a problems and should halt. */ msr = rdmsr(MC_CF07_DATA); - if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == + if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { print_emerg("No memory in the system\n"); post_code(ERROR_NO_DIMMS); |