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Diffstat (limited to 'src/northbridge/amd/lx/raminit.c')
-rw-r--r--src/northbridge/amd/lx/raminit.c402
1 files changed, 194 insertions, 208 deletions
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 39ae1de577..fd496d80f4 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -22,9 +22,13 @@
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536.h"
-static const unsigned char NumColAddr[] = {0x00,0x10,0x11,0x00,0x00,0x00,0x00,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F};
+static const unsigned char NumColAddr[] = {
+ 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+};
-static void auto_size_dimm(unsigned int dimm){
+static void auto_size_dimm(unsigned int dimm)
+{
uint32_t dimm_setting;
uint16_t dimm_size;
uint8_t spd_byte;
@@ -33,60 +37,58 @@ static void auto_size_dimm(unsigned int dimm){
dimm_setting = 0;
/* Check that we have a dimm */
- if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF){
+ if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
return;
-}
+ }
/* Field: Module Banks per DIMM */
/* EEPROM byte usage: (5) Number of DIMM Banks */
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
- if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)){
+ if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
print_debug("Number of module banks not compatible\r\n");
POST_CODE(ERROR_BANK_SET);
__asm__ __volatile__("hlt\n");
}
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
-
/* Field: Banks per SDRAM device */
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
- if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)){
+ if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
print_debug("Number of device banks not compatible\r\n");
POST_CODE(ERROR_BANK_SET);
__asm__ __volatile__("hlt\n");
}
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
-
/*; Field: DIMM size
- *; EEPROM byte usage: (3) Number or Row Addresses
- *; (4) Number of Column Addresses
- *; (5) Number of DIMM Banks
- *; (31) Module Bank Density
- *; Size = Module Density * Module Banks
+ *; EEPROM byte usage: (3) Number or Row Addresses
+ *; (4) Number of Column Addresses
+ *; (5) Number of DIMM Banks
+ *; (31) Module Bank Density
+ *; Size = Module Density * Module Banks
*/
- if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)){
+ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
+ || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
print_debug("Assymetirc DIMM not compatible\r\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
__asm__ __volatile__("hlt\n");
}
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
- dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out*/
- dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top*/
+ dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
+ dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
- /* Module Density * Module Banks */
- dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
+ /* Module Density * Module Banks */
+ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
dimm_size = __builtin_ctz(dimm_size);
- if (dimm_size > 8){ /* 8 is 1GB only support 1GB per DIMM */
+ if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
print_debug("Only support up to 1 GB per DIMM\r\n");
POST_CODE(ERROR_DENSITY_DIMM);
__asm__ __volatile__("hlt\n");
}
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
-
/*; Field: PAGE size
*; EEPROM byte usage: (4) Number of Column Addresses
*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
@@ -116,98 +118,98 @@ static void auto_size_dimm(unsigned int dimm){
POST_CODE(ERROR_SET_PAGE);
__asm__ __volatile__("hlt\n");
}
- spd_byte -=7;
- if (spd_byte > 5){ /* if the value is above 6 it means >12 address lines */
- spd_byte = 7; /* which means >32k so set to disabled */
+ spd_byte -= 7;
+ if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */
+ spd_byte = 7; /* which means >32k so set to disabled */
}
- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
+ dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
msr = rdmsr(MC_CF07_DATA);
- if (dimm == DIMM0){
+ if (dimm == DIMM0) {
msr.hi &= 0xFFFF0000;
msr.hi |= dimm_setting;
- }else{
+ } else {
msr.hi &= 0x0000FFFF;
msr.hi |= dimm_setting << 16;
}
wrmsr(MC_CF07_DATA, msr);
}
-
-static void checkDDRMax(void){
+static void checkDDRMax(void)
+{
uint8_t spd_byte0, spd_byte1;
uint16_t speed;
- /* PC133 identifier */
+ /* PC133 identifier */
spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
/* I don't think you need this check.
- if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
- print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
- POST_CODE(POST_PLL_MEM_FAIL);
- __asm__ __volatile__("hlt\n");
- }*/
-
+ if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
+ print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
+ POST_CODE(POST_PLL_MEM_FAIL);
+ __asm__ __volatile__("hlt\n");
+ } */
/* Use the slowest DIMM */
- if (spd_byte0 < spd_byte1){
+ if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- speed = 2*((10000/(((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
+ speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F))));
/* current speed > max speed? */
- if (GeodeLinkSpeed() > speed){
+ if (GeodeLinkSpeed() > speed) {
print_debug("DIMM overclocked. Check GeodeLink Speed\r\n");
POST_CODE(POST_PLL_MEM_FAIL);
__asm__ __volatile__("hlt\n");
}
}
+const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
-const uint16_t REF_RATE[] = {15, 3, 7, 31, 62, 125}; /* ns */
-
-static void set_refresh_rate(void){
+static void set_refresh_rate(void)
+{
uint8_t spd_byte0, spd_byte1;
uint16_t rate0, rate1;
msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
spd_byte0 &= 0xF;
- if (spd_byte0 > 5){
+ if (spd_byte0 > 5) {
spd_byte0 = 5;
}
rate0 = REF_RATE[spd_byte0];
spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
spd_byte1 &= 0xF;
- if (spd_byte1 > 5){
+ if (spd_byte1 > 5) {
spd_byte1 = 5;
}
rate1 = REF_RATE[spd_byte1];
/* Use the faster rate (lowest number) */
- if (rate0 > rate1){
+ if (rate0 > rate1) {
rate0 = rate1;
}
- msr = rdmsr(MC_CF07_DATA);
- msr.lo|= ((rate0 * (GeodeLinkSpeed()/2))/16) << CF07_LOWER_REF_INT_SHIFT;
- wrmsr(MC_CF07_DATA, msr);
- }
-
+ msr = rdmsr(MC_CF07_DATA);
+ msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
+ << CF07_LOWER_REF_INT_SHIFT;
+ wrmsr(MC_CF07_DATA, msr);
+}
-const uint8_t CASDDR[] = {5, 5, 2, 6, 3, 7, 4, 0}; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
+const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
-static void setCAS(void){
+static void setCAS(void)
+{
/*;*****************************************************************************
;*
;* setCAS
@@ -236,226 +238,220 @@ static void setCAS(void){
/************************** DIMM0 **********************************/
casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
- if (casmap0 != 0xFF){
+ if (casmap0 != 0xFF) {
/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
- if(spd_byte != 0){
+ if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
- if (dimm_speed >= glspeed){
+ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +
+ (spd_byte & 0x0F)));
+ if (dimm_speed >= glspeed) {
/* IF -1 timing is supported, check -1 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
- if(spd_byte != 0){
+ if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
- if (dimm_speed <= glspeed){
+ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+ if (dimm_speed <= glspeed) {
/* set we can use -.5 timing but not -1 */
- spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
+ /* just want bits in the lower byte since we have to cast to a 32 */
casmap0 &= 0xFF << (--spd_byte);
}
- } /*MIN_CYCLE_10 !=0 */
- }
- else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
- spd_byte = 31 - __builtin_clz((uint32_t)casmap0); /* just want bits in the lower byte since we have to cast to a 32 */
+ } /*MIN_CYCLE_10 !=0 */
+ } else {
+ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
+ /* just want bits in the lower byte since we have to cast to a 32 */
casmap0 &= 0xFF << (spd_byte);
}
- } /*MIN_CYCLE_05 !=0 */
- }
- else{ /* No DIMM */
- casmap0=0;
+ } /*MIN_CYCLE_05 !=0 */
+ } else { /* No DIMM */
+ casmap0 = 0;
}
/************************** DIMM1 **********************************/
casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES);
- if (casmap1 != 0xFF){
+ if (casmap1 != 0xFF) {
/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND);
- if(spd_byte != 0){
+ if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
- if (dimm_speed >= glspeed){
+ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+ if (dimm_speed >= glspeed) {
/* IF -1 timing is supported, check -1 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
- if(spd_byte != 0){
+ if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- dimm_speed = 2*(10000/(((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
- if (dimm_speed <= glspeed){
+ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
+ if (dimm_speed <= glspeed) {
/* set we can use -.5 timing but not -1 */
- spd_byte =31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
+ /* just want bits in the lower byte since we have to cast to a 32 */
casmap1 &= 0xFF << (--spd_byte);
}
- } /*MIN_CYCLE_10 !=0 */
- }
- else{ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
- spd_byte = 31 - __builtin_clz((uint32_t)casmap1); /* just want bits in the lower byte since we have to cast to a 32 */
+ } /*MIN_CYCLE_10 !=0 */
+ } else {
+ /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
+ /* just want bits in the lower byte since we have to cast to a 32 */
casmap1 &= 0xFF << (spd_byte);
}
- } /*MIN_CYCLE_05 !=0 */
- }
- else{ /* No DIMM */
- casmap1=0;
+ } /*MIN_CYCLE_05 !=0 */
+ } else { /* No DIMM */
+ casmap1 = 0;
}
/********************* CAS_LAT MAP COMPARE ***************************/
- if (casmap0 == 0){
- spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap1)];
- }
- else if (casmap1 == 0){
- spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)];
- }
- else if ((casmap0 &= casmap1)){
- spd_byte = CASDDR[__builtin_ctz((uint32_t)casmap0)];
- }
- else{
+ if (casmap0 == 0) {
+ spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)];
+ } else if (casmap1 == 0) {
+ spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
+ } else if ((casmap0 &= casmap1)) {
+ spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
+ } else {
print_debug("DIMM CAS Latencies not compatible\r\n");
POST_CODE(ERROR_DIFF_DIMMS);
__asm__ __volatile__("hlt\n");
}
-
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
wrmsr(MC_CF8F_DATA, msr);
}
-
-static void set_latencies(void){
+static void set_latencies(void)
+{
uint32_t memspeed, dimm_setting;
uint8_t spd_byte0, spd_byte1;
msr_t msr;
- memspeed = GeodeLinkSpeed()/2;
- dimm_setting=0;
+ memspeed = GeodeLinkSpeed() / 2;
+ dimm_setting = 0;
/* MC_CF8F setup */
/* tRAS */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
- if (spd_byte0 < spd_byte1){
+ if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
- spd_byte1 = (spd_byte0 * memspeed)/1000;
- if(((spd_byte0 * memspeed)%1000)){
+ spd_byte1 = (spd_byte0 * memspeed) / 1000;
+ if (((spd_byte0 * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
-
/* tRP */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
- if (spd_byte0 < spd_byte1){
+ if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
- spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000;
- if((((spd_byte0 >> 2) * memspeed)%1000)){
+ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+ if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
-
/* tRCD */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
- if (spd_byte0 < spd_byte1){
+ if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
- spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000;
- if((((spd_byte0 >> 2) * memspeed)%1000)){
+ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+ if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
-
/* tRRD */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
- if (spd_byte0 < spd_byte1){
+ if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
- spd_byte1 = ((spd_byte0 >> 2) * memspeed)/1000;
- if((((spd_byte0 >> 2) * memspeed)%1000)){
+ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+ if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
-
/* tRC = tRP + tRAS */
- dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) \
- << CF8F_LOWER_ACT2ACTREF_SHIFT;
-
+ dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
+ ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
+ << CF8F_LOWER_ACT2ACTREF_SHIFT;
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= 0xF00000FF;
msr.lo |= dimm_setting;
- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
+ msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr);
/* MC_CF1017 setup */
/* tRFC */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
- if (spd_byte0 < spd_byte1){
+ if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
- if (spd_byte0){
+ if (spd_byte0) {
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
- spd_byte1 = (spd_byte0 * memspeed)/1000;
- if(((spd_byte0 * memspeed)%1000)){
+ spd_byte1 = (spd_byte0 * memspeed) / 1000;
+ if (((spd_byte0 * memspeed) % 1000)) {
++spd_byte1;
}
- }
- else{ /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
+ } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
}
- dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
+ dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
msr = rdmsr(MC_CF1017_DATA);
msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
msr.lo |= dimm_setting;
wrmsr(MC_CF1017_DATA, msr);
/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
- if (memspeed > 198){
+ if (memspeed > 198) {
msr = rdmsr(MC_CF1017_DATA);
msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
@@ -463,41 +459,45 @@ static void set_latencies(void){
}
}
-static void set_extended_mode_registers(void){
+static void set_extended_mode_registers(void)
+{
uint8_t spd_byte0, spd_byte1;
msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
- if (spd_byte0 == 0xFF){
- spd_byte0=0;
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
- if (spd_byte1 == 0xFF){
- spd_byte1=0;
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
}
spd_byte1 &= spd_byte0;
msr = rdmsr(MC_CF07_DATA);
- if (spd_byte1 & 1){ /* Drive Strength Control */
+ if (spd_byte1 & 1) { /* Drive Strength Control */
msr.lo |= CF07_LOWER_EMR_DRV_SET;
}
- if (spd_byte1 & 2){ /* FET Control */
+ if (spd_byte1 & 2) { /* FET Control */
msr.lo |= CF07_LOWER_EMR_QFC_SET;
}
wrmsr(MC_CF07_DATA, msr);
}
-static void EnableMTest (void){
+static void EnableMTest(void)
+{
msr_t msr;
msr = rdmsr(GLCP_DELAY_CONTROLS);
- msr.hi &= ~(7 << 20); /* clear bits 54:52 */
- if (GeodeLinkSpeed() < 200){
+ msr.hi &= ~(7 << 20); /* clear bits 54:52 */
+ if (GeodeLinkSpeed() < 200) {
msr.hi |= 2 << 20;
}
wrmsr(GLCP_DELAY_CONTROLS, msr);
msr = rdmsr(MC_CFCLK_DBUG);
- msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET | CFCLK_UPPER_MTST_RBEX_EN_SET;
+ msr.hi |=
+ CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
+ CFCLK_UPPER_MTST_RBEX_EN_SET;
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
@@ -513,10 +513,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
msrnum = MC_CF1017_DATA;
msr = rdmsr(msrnum);
msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
- if (GeodeLinkSpeed() < 334){
+ if (GeodeLinkSpeed() < 334) {
msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
- }
- else{
+ } else {
msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
}
wrmsr(msrnum, msr);
@@ -525,50 +524,49 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
msr.lo &= ~0xF0;
- msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */
+ msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */
wrmsr(msrnum, msr);
/* Memory Interleave: Set HOI here otherwise default is LOI */
/* msrnum = MC_CF8F_DATA;
- msr = rdmsr(msrnum);
- msr.hi |= CF8F_UPPER_HOI_LOI_SET;
- wrmsr(msrnum, msr); */
+ msr = rdmsr(msrnum);
+ msr.hi |= CF8F_UPPER_HOI_LOI_SET;
+ wrmsr(msrnum, msr); */
}
-
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t spd_byte;
- POST_CODE(POST_MEM_SETUP); // post_70h
+ POST_CODE(POST_MEM_SETUP); // post_70h
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
/* Check DIMM is not Register and not Buffered DIMMs. */
- if ((spd_byte != 0xFF) && (spd_byte & 3) ){
+ if ((spd_byte != 0xFF) && (spd_byte & 3)) {
print_debug("DIMM0 NOT COMPATIBLE\r\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
__asm__ __volatile__("hlt\n");
}
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
- if ((spd_byte != 0xFF) && (spd_byte & 3)){
+ if ((spd_byte != 0xFF) && (spd_byte & 3)) {
print_debug("DIMM1 NOT COMPATIBLE\r\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
__asm__ __volatile__("hlt\n");
}
- POST_CODE(POST_MEM_SETUP2); // post_72h
+ POST_CODE(POST_MEM_SETUP2); // post_72h
/* Check that the memory is not overclocked. */
checkDDRMax();
/* Size the DIMMS */
- POST_CODE(POST_MEM_SETUP3); // post_73h
+ POST_CODE(POST_MEM_SETUP3); // post_73h
auto_size_dimm(DIMM0);
- POST_CODE(POST_MEM_SETUP4); // post_74h
+ POST_CODE(POST_MEM_SETUP4); // post_74h
auto_size_dimm(DIMM1);
/* Set CAS latency */
- POST_CODE(POST_MEM_SETUP5); // post_75h
+ POST_CODE(POST_MEM_SETUP5); // post_75h
setCAS();
/* Set all the other latencies here (tRAS, tRP....) */
@@ -601,65 +599,59 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
;* 9) MRS w/ memory config & reset DLL clear
;* 8) DDR SDRAM ready for normal operation
;********************************************************************/
- POST_CODE(POST_MEM_ENABLE); // post_76h
+ POST_CODE(POST_MEM_ENABLE); // post_76h
/* Only enable MTest for TLA memory debug */
- /*EnableMTest();*/
+ /*EnableMTest(); */
/* If both Page Size = "Not Installed" we have a problems and should halt. */
msr = rdmsr(MC_CF07_DATA);
- if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) \
- == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))){
+ if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
+ ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
print_debug("No memory in the system\r\n");
POST_CODE(ERROR_NO_DIMMS);
__asm__ __volatile__("hlt\n");
}
- /* Set CKEs */
+ /* Set CKEs */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
wrmsr(msrnum, msr);
-
/* Force Precharge All on next command, EMRS */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
- wrmsr(msrnum,msr);
-
+ wrmsr(msrnum, msr);
/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
- msrnum = MC_CF07_DATA;
+ msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
wrmsr(msrnum, msr);
msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
wrmsr(msrnum, msr);
-
/* Clear Force Precharge All */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
-
/* MRS Reset DLL - set */
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
- wrmsr(msrnum,msr);
+ wrmsr(msrnum, msr);
msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
wrmsr(msrnum, msr);
-
/* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
/* Wait 2 PORT61 ticks. between 15us and 30us */
/* This would be endless if the timer is stuck. */
- while ((inb(0x61))); /* find the first edge */
- while (!(~inb(0x61)));
-
+ while ((inb(0x61))) ; /* find the first edge */
+ while (!(~inb(0x61))) ;
/* Force Precharge All on the next command, auto-refresh */
msrnum = MC_CFCLK_DBUG;
@@ -667,7 +659,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
-
/* Manually AUTO refresh #1 */
/* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
msrnum = MC_CF07_DATA;
@@ -683,7 +674,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
wrmsr(msrnum, msr);
-
/* Manually AUTO refresh */
/* The MC should insert the right delay between the refreshes */
msrnum = MC_CF07_DATA;
@@ -693,7 +683,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~CF07_LOWER_REF_TEST_SET;
wrmsr(msrnum, msr);
-
/* MRS Reset DLL - clear */
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
@@ -702,17 +691,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
wrmsr(msrnum, msr);
-
/* Allow MC to tristate during idle cycles with MTEST OFF */
msrnum = MC_CFCLK_DBUG;
msr = rdmsr(msrnum);
msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(msrnum, msr);
-
/* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
msr = rdmsr(MC_CF07_DATA);
- if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) == (7 << CF07_UPPER_D1_PSZ_SHIFT)){
+ if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
+ (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
msrnum = GLCP_DELAY_CONTROLS;
msr = rdmsr(msrnum);
msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */
@@ -720,11 +708,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
/* Set PMode0 Sensitivity Counter */
- msr.lo = 0; /* pmode 0=0 most aggressive */
+ msr.lo = 0; /* pmode 0=0 most aggressive */
msr.hi = 0x200; /* pmode 1=200h */
wrmsr(MC_CF_PMCTR, msr);
-
/* Set PMode1 Up delay enable */
msrnum = MC_CF1017_DATA;
msr = rdmsr(msrnum);
@@ -732,15 +719,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(msrnum, msr);
print_debug("DRAM controller init done.\r\n");
- POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
+ POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
/* make sure there is nothing stale in the cache */
- /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n");*/
+ /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
/* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */
volatile unsigned long *ptr;
- for (i=0;i<5;i++) {
+ for (i = 0; i < 5; i++) {
ptr = (void *)i;
*ptr = (unsigned long)i;
}
@@ -751,19 +738,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
if ((msr.lo & 0x7FF) == 0x104) {
/* If you had it you would need to clear out the fail boot count flag */
- /* (depending on where it counts from etc).*/
+ /* (depending on where it counts from etc). */
/* The reset we are about to perform clears the PM_SSC register in the */
- /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
- /* it would do a normal boot */
+ /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
+ /* it would do a normal boot */
/* Reset the system */
msrnum = MDD_SOFT_RESET;
msr = rdmsr(msrnum);
msr.lo |= 1;
wrmsr(msrnum, msr);
-}
+ }
print_debug("RAM DLL lock\r\n");
-
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-01 13:16:57 +0000