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-rw-r--r--src/northbridge/amd/gx1/Config.lb2
-rw-r--r--src/northbridge/amd/gx1/northbridge.c12
2 files changed, 14 insertions, 0 deletions
diff --git a/src/northbridge/amd/gx1/Config.lb b/src/northbridge/amd/gx1/Config.lb
index 16463e0ccd..adb96c3c64 100644
--- a/src/northbridge/amd/gx1/Config.lb
+++ b/src/northbridge/amd/gx1/Config.lb
@@ -1,2 +1,4 @@
+uses HAVE_HIGH_TABLES
config chip.h
driver northbridge.o
+default HAVE_HIGH_TABLES=1
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 247c24304e..63cc003df0 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -126,6 +126,11 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
@@ -168,6 +173,13 @@ static void pci_domain_set_resources(device_t dev)
*/
tolmk = tomk;
}
+
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
+
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, tolmk);