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path: root/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index e098d7f527..1312b34bce 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -5631,7 +5631,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct)
{
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
mct_ProgramODT_D(pMCTstat, pDCTstat, dct);
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
@@ -5641,6 +5645,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
u32 dword;
u32 dev = pDCTstat->dev_dct;
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
@@ -5955,6 +5961,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
}
}
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,