diff options
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctpro_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctpro_d.c | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index bdfff046f4..a6d6bad164 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +20,7 @@ void EarlySampleSupport_D(void) u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) { - u32 tmp; + uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { val &= 0x0FFFFFFF; @@ -38,7 +39,7 @@ u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val) * ( F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B * FIXME: check if this is still required. */ - u32 tmp; + uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { if(!(val & (3<<12) )) @@ -50,7 +51,7 @@ u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val) void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct) { - u32 tmp; + uint64_t tmp; u32 reg; u32 reg_off; u32 dev; @@ -92,7 +93,7 @@ void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat, * FIXME: check this. */ - u32 tmp; + uint64_t tmp; u32 dev; u32 reg; u32 val; @@ -139,10 +140,9 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, u32 index; u32 reg; u32 val; - u32 tmp; + uint64_t tmp; u32 Channel; - tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { @@ -202,7 +202,7 @@ u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value) u32 index_reg; u32 index; u32 val; - u32 tmp; + uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { @@ -233,7 +233,7 @@ void SyncSetting(struct DCTStatStruc *pDCTstat) * Silicon Status: Fix TBD */ - u32 tmp; + uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { pDCTstat->CH_ODC_CTL[1] = pDCTstat->CH_ODC_CTL[0]; @@ -274,7 +274,7 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) { - u32 tmp; + uint64_t tmp; u32 Speed; u32 ch, ch_start, ch_end; u32 index_reg; @@ -282,7 +282,6 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) u32 dev; u32 val; - tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { Speed = pDCTstat->Speed; @@ -327,7 +326,7 @@ static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, u8 ChipSel, u8 *result) { u8 ByteLane; - u32 tmp; + uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { |