diff options
Diffstat (limited to 'src/northbridge/amd/amdk8')
| -rw-r--r-- | src/northbridge/amd/amdk8/Config.lb | 20 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/amdk8.h | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 24 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/debug.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/early_ht.c | 20 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/exit_from_self.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/get_sblk_pci1234.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/incoherent_ht.c | 56 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/misc_control.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 44 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 16 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f.c | 40 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 22 |
13 files changed, 127 insertions, 127 deletions
diff --git a/src/northbridge/amd/amdk8/Config.lb b/src/northbridge/amd/amdk8/Config.lb index bb38d7319a..40de82e04d 100644 --- a/src/northbridge/amd/amdk8/Config.lb +++ b/src/northbridge/amd/amdk8/Config.lb @@ -1,22 +1,22 @@ -uses AGP_APERTURE_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_HIGH_TABLES -uses K8_REV_F_SUPPORT +uses CONFIG_AGP_APERTURE_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_HIGH_TABLES +uses CONFIG_K8_REV_F_SUPPORT -default AGP_APERTURE_SIZE=0x4000000 -default HAVE_HIGH_TABLES=1 +default CONFIG_AGP_APERTURE_SIZE=0x4000000 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o driver misc_control.o -if K8_REV_F_SUPPORT +if CONFIG_K8_REV_F_SUPPORT makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end else @@ -24,13 +24,13 @@ else makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object amdk8_acpi.o end diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 5af58dea45..f03b93c9b5 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -2,7 +2,7 @@ #define AMDK8_H -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #include "amdk8_f.h" #else #include "amdk8_pre_f.h" diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index d24a83c68f..bb5b2f7dd2 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -88,8 +88,8 @@ #define TRY_HIGH_FIRST 0 #endif -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef K8_HT_CHECK_PENDING_LINK @@ -104,8 +104,8 @@ #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 #endif -#ifndef ENABLE_APIC_EXT_ID - #define ENABLE_APIC_EXT_ID 0 +#ifndef CONFIG_ENABLE_APIC_EXT_ID + #define CONFIG_ENABLE_APIC_EXT_ID 0 #endif @@ -161,7 +161,7 @@ static void disable_probes(void) static void enable_apic_ext_id(u8 node) { -#if ENABLE_APIC_EXT_ID==1 +#if CONFIG_ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?" u32 val; @@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) #endif { @@ -1591,13 +1591,13 @@ static unsigned verify_dualcore(unsigned nodes) static void coherent_ht_finalize(unsigned nodes) { unsigned node; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 int rev_a0; #endif #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if ((!HAVE_OPTION_TABLE) || + if ((!CONFIG_HAVE_OPTION_TABLE) || read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ total_cpus = verify_dualcore(nodes); } @@ -1613,7 +1613,7 @@ static void coherent_ht_finalize(unsigned nodes) */ print_spew("coherent_ht_finalize\r\n"); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { @@ -1644,7 +1644,7 @@ static void coherent_ht_finalize(unsigned nodes) (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); @@ -1664,7 +1664,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) device_t dev; uint32_t cmd; dev = NODE_MC(node); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 66 diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 4ed376ae07..a445f253c7 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -91,7 +91,7 @@ static void dump_pci_device(unsigned dev) print_debug("\r\n"); } -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6cfecbddf7..bf80ef833e 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -4,8 +4,8 @@ // only for sb ht chain static void enumerate_ht_chain(void) { -#if HT_CHAIN_UNITID_BASE != 0 -/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ +#if CONFIG_HT_CHAIN_UNITID_BASE != 0 +/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. * On most boards this just happens. If a cpu has multiple @@ -14,8 +14,8 @@ static void enumerate_ht_chain(void) */ unsigned next_unitid, last_unitid; device_t dev; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; // except host_bridge @@ -23,7 +23,7 @@ static void enumerate_ht_chain(void) #endif dev = PCI_DEV(0,0,0); - next_unitid = HT_CHAIN_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { uint32_t id; uint8_t hdr_type, pos; @@ -63,10 +63,10 @@ static void enumerate_ht_chain(void) unsigned ctrl, ctrl_off; device_t devx; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -126,13 +126,13 @@ static void enumerate_ht_chain(void) out: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags); } #endif diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index f8c6744ed1..5c7ba00ff9 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -156,7 +156,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 85dd403a43..737f33b48d 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -176,7 +176,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * Just put all the possible HT Node/link to the list tp pci1234[] in * src/mainboard/<vendor>/<mainboard>get_bus_conf.c * - * Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if + * Also don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc (FIXME what else) if * you have too many SSDTs * * What about co-processor in socket 1 on a 2 way system? Or socket 2 and diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 74c9f4fe4f..4c30a098e1 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -7,8 +7,8 @@ #include <device/pci_ids.h> #include <device/hypertransport_def.h> -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef RAMINIT_SYSINFO @@ -85,14 +85,14 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid device_t dev; //actually, only for one HT device HT chain, and unitid is 0 -#if HT_CHAIN_UNITID_BASE == 0 +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 if(offset_unitid) { return; } #endif /* Check if is already collapsed */ - if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) { + if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { uint32_t id; dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -154,8 +154,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } @@ -303,7 +303,7 @@ static int ht_optimize_link( return needs_reset; } -#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) +#if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) #if RAMINIT_SYSINFO == 1 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); @@ -425,7 +425,7 @@ static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned o static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) #endif { - //even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link + //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link uint8_t next_unitid, last_unitid; unsigned uoffs; @@ -434,8 +434,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of int reset_needed = 0; #endif -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; @@ -443,7 +443,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #endif uoffs = PCI_HT_HOST_OFFS; - next_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE:1; + next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1; do { uint32_t id; @@ -500,11 +500,11 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid) { if(next_unitid>= (bus ? 0x20:0x18) ) { if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -560,18 +560,18 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } while (last_unitid != next_unitid ); -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: #endif end_of_chain: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { uint16_t flags; int i; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); #if RAMINIT_SYSINFO == 1 @@ -580,11 +580,11 @@ end_of_chain: ; { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + link_pair->udev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); continue; } if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + link_pair->dev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); } } #endif @@ -605,7 +605,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif { unsigned offset_unitid = 0; -#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif @@ -618,7 +618,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) /* Make certain the HT bus is not enumerated */ ht_collapse_previous_enumeration(0, 0); -#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif @@ -666,11 +666,11 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) uint8_t val; unsigned devn = 1; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif - devn = HT_CHAIN_UNITID_BASE; + devn = CONFIG_HT_CHAIN_UNITID_BASE; #endif reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); @@ -781,7 +781,7 @@ static int ht_setup_chains(uint8_t ht_c_num) unsigned regpos; uint32_t dword; uint8_t busn; - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) + #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) unsigned bus; #endif unsigned offset_unitid = 0; @@ -799,8 +799,8 @@ static int ht_setup_chains(uint8_t ht_c_num) pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif offset_unitid = 1; @@ -818,7 +818,7 @@ static int ht_setup_chains(uint8_t ht_c_num) reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not #endif - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) + #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ bus = busn; // we need 32 bit #if RAMINIT_SYSINFO == 1 diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 1090d61b07..7c35082705 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -53,7 +53,7 @@ static void mcf3_read_resources(device_t dev) if (iommu) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?AGP_APERTURE_SIZE:1; + resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ @@ -121,7 +121,7 @@ static void misc_control_init(struct device *dev) cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd ); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 58 diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index b6c0f7c8c0..c51bc21b03 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -155,12 +155,12 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here min_bus = max; } - #if SB_HT_CHAIN_ON_BUS0 > 1 + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 else { min_bus = ((max>>6) + 1) * 0x40; @@ -257,8 +257,8 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) if(nodeid==0) { sblink = (pci_read_config32(dev, 0x64)>>8) & 3; -#if SB_HT_CHAIN_ON_BUS0 > 0 - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 @@ -266,12 +266,12 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) } for(link = 0; link < dev->links; link++) { -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; @@ -743,7 +743,7 @@ static uint32_t find_pci_tolm(struct bus *bus) #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -755,7 +755,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < FX_DEVS; i++) { @@ -893,7 +893,7 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i) } #endif -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -907,7 +907,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long mmio_basek; uint32_t pci_tolm; int i, idx; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; unsigned reset_memhole = 1; #endif @@ -991,12 +991,12 @@ static void pci_domain_set_resources(device_t dev) mmio_basek &= ~((64*1024) - 1); #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { #endif @@ -1010,13 +1010,13 @@ static void pci_domain_set_resources(device_t dev) //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { - if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some uint32_t basek_pri; for (i = 0; i < FX_DEVS; i++) { @@ -1037,7 +1037,7 @@ static void pci_domain_set_resources(device_t dev) #endif } -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 } // is_cpu_pre_e0 #endif @@ -1077,7 +1077,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; @@ -1087,9 +1087,9 @@ static void pci_domain_set_resources(device_t dev) } #endif } - #if HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if(!is_cpu_pre_e0() ) #endif sizek += hoist_memory(mmio_basek,i); @@ -1111,7 +1111,7 @@ static void pci_domain_set_resources(device_t dev) if (sizek) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { @@ -1211,7 +1211,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) sysconf.enabled_apic_ext_id = 1; if(bsp_apicid == 0) { /* bsp apic id is not changed */ - sysconf.apicid_offset = APIC_ID_OFFSET; + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; } else { sysconf.lift_bsp_apicid = 1; @@ -1263,7 +1263,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) // That is the typical case if(j == 0 ){ - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index e55f4b898f..83ae83032a 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -553,7 +553,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (HAVE_OPTION_TABLE && + if (CONFIG_HAVE_OPTION_TABLE && read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } @@ -867,7 +867,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else @@ -1104,7 +1104,7 @@ static void order_dimms(const struct mem_controller *ctrl) { unsigned long tom_k, base_k; - if ((!HAVE_OPTION_TABLE) || + if ((!CONFIG_HAVE_OPTION_TABLE) || read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { @@ -1408,7 +1408,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { + if (CONFIG_HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; @@ -2111,7 +2111,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) return; } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2170,10 +2170,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), * we need to decrease it. @@ -2328,7 +2328,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 // init hw mem hole here /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ if (!is_cpu_pre_e0()) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 37398a8d23..0ad5e4758a 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -882,11 +882,11 @@ static void set_dimm_size(const struct mem_controller *ctrl, if (base0) { uint32_t dword; uint32_t ClkDis0; -#if CPU_SOCKET_TYPE == 0x10 /* L1 */ +#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */ ClkDis0 = DTL_MemClkDis0; -#elif CPU_SOCKET_TYPE == 0x11 /* AM2 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */ ClkDis0 = DTL_MemClkDis0_AM2; -#elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */ ClkDis0 = DTL_MemClkDis0_S1g1; #endif @@ -1066,7 +1066,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else @@ -1452,7 +1452,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ -#if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 +#if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12 u8 mux_cap = 1; #else u8 mux_cap = 0; @@ -2341,7 +2341,7 @@ static void set_DramTerm(const struct mem_controller *ctrl, } -#if DIMM_SUPPORT == 0x0204 +#if CONFIG_DIMM_SUPPORT == 0x0204 odt = 0x2; /* 150 ohms */ #endif @@ -2512,7 +2512,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * long dimm_mask = meminfo->dimm_mask & 0x0f; -#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; @@ -2536,7 +2536,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * #endif -#if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00; @@ -2576,7 +2576,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif -#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; @@ -2658,7 +2658,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif -#if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ if (SlowAccessMode) { set_SlowAccessMode(ctrl); } @@ -2689,7 +2689,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE==0x10 //only need to set for reg and x8 uint32_t dch; @@ -2880,7 +2880,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, #include "raminit_f_dqs.c" -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2941,10 +2941,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; @@ -3143,7 +3143,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); @@ -3175,7 +3175,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 dqs_timing(controllers, ctrl, tsc0, sysinfo); #else @@ -3183,7 +3183,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, #endif #else -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 /* need to enable mtrr, so dqs training could access the test address */ setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -3195,18 +3195,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dqs_timing(i, &ctrl[i], sysinfo, 1); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 break; // only train the first node with ram #endif } -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 clear_mtrr_dqs(sysinfo->tom2_k); #endif #endif -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 wait_all_core0_mem_trained(sysinfo); #endif diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index e58a63053d..2764e606be 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -78,7 +78,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i uint32_t mem_base; unsigned nodeid = ctrl->node_id; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 uint32_t hole_reg; #endif @@ -91,7 +91,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i mem_base &= 0xffff0000; dword += mem_base; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 hole_reg = sysinfo->hole_reg[nodeid]; if(hole_reg & 1) { unsigned hole_startk; @@ -855,7 +855,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st //restore SSE2 setting disable_sse2(); -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif @@ -1702,7 +1702,7 @@ static unsigned int range_to_mtrr(unsigned int reg, align = max_align; } sizek = 1 << align; -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -1921,7 +1921,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev) pci_write_config32(dev, DRAM_CONFIG_HIGH, reg); } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 static void dqs_timing(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo) #else @@ -2007,7 +2007,7 @@ out: #endif -#if MEM_TRAIN_SEQ > 0 +#if CONFIG_MEM_TRAIN_SEQ > 0 static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned v) { @@ -2018,7 +2018,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info if(sysinfo->mem_trained[i] != 0x80) return; -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -2064,7 +2064,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } out: -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 clear_mtrr_dqs(sysinfo->tom2_k); #endif @@ -2081,7 +2081,7 @@ out: } #endif -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy @@ -2094,7 +2094,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr); static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { @@ -2105,7 +2105,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else - memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE); + memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 |