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path: root/src/northbridge/amd/amdk8/raminit_f.c
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Diffstat (limited to 'src/northbridge/amd/amdk8/raminit_f.c')
-rw-r--r--src/northbridge/amd/amdk8/raminit_f.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index a97989687a..39c5ad842c 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -33,11 +33,11 @@
#include "raminit.h"
#include "f.h"
#include <spd_ddr2.h>
-#if CONFIG_HAVE_OPTION_TABLE
+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
-#if CONFIG_DEBUG_RAM_SETUP
+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
#define printk_raminit(args...) printk(BIOS_DEBUG, args)
#else
#define printk_raminit(args...)
@@ -845,7 +845,7 @@ static void set_dimm_size(const struct mem_controller *ctrl,
/* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
@@ -873,7 +873,7 @@ static void set_dimm_size(const struct mem_controller *ctrl,
} else {
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
dword &= ~(ClkDis0 >> index);
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
@@ -883,7 +883,7 @@ static void set_dimm_size(const struct mem_controller *ctrl,
if (meminfo->is_Width128) { // ChannelA+B
dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
dword &= ~(ClkDis0 >> index);
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
dword &= ~(ClkDis0 >> (index+2));
}
@@ -936,7 +936,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
}
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
map &= ~(0xf << ((index + 2) * 4));
}
@@ -947,7 +947,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
unsigned temp_map;
temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];
map |= temp_map << (index*4);
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (sz->rank == 4) {
map |= temp_map << ((index + 2) * 4);
}
@@ -1291,7 +1291,7 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
} else {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (meminfo->sz[index].rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@ -2173,7 +2173,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl,
static void set_4RankRDimm(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
int value;
int i;
long dimm_mask = meminfo->dimm_mask;
@@ -2213,7 +2213,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
uint32_t mask_single_rank;
uint32_t mask_page_1k;
int value;
-#if CONFIG_QRANK_DIMM_SUPPORT
+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
int rank;
#endif
@@ -2246,20 +2246,20 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
- #if CONFIG_QRANK_DIMM_SUPPORT
+ #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
rank = meminfo->sz[i].rank;
#endif
if (value == 4) {
mask_x4 |= (1<<i);
- #if CONFIG_QRANK_DIMM_SUPPORT
+ #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (rank == 4) {
mask_x4 |= 1<<(i+2);
}
#endif
} else if (value == 16) {
mask_x16 |= (1<<i);
- #if CONFIG_QRANK_DIMM_SUPPORT
+ #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)
if (rank == 4) {
mask_x16 |= 1<<(i+2);
}
@@ -2348,7 +2348,7 @@ static void set_ecc(const struct mem_controller *ctrl,
dcl &= ~DCL_DimmEccEn;
}
#else // CMOS_VSTART_ECC_memory not defined
-#if !CONFIG_ECC_MEMORY
+#if !IS_ENABLED(CONFIG_ECC_MEMORY)
dcl &= ~DCL_DimmEccEn;
#endif
#endif
@@ -2932,7 +2932,7 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)
/* We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some */
uint32_t basek_pri;