1 files changed, 43 insertions, 39 deletions

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 0fe2cc5460..4938c453d7 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -15,6 +15,8 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <part/hard_reset.h>
+#include <pc80/mc146818rtc.h>
+#include <bitops.h>
 #include "./cpu_rev.c"
 #include "amdk8.h"
 
@@ -35,7 +37,7 @@
 static void mcf3_read_resources(device_t dev)
 {
 	struct resource *resource;
-
+	unsigned char iommu;
 	/* Read the generic PCI resources */
 	pci_dev_read_resources(dev);
 
@@ -43,58 +45,60 @@ static void mcf3_read_resources(device_t dev)
 	if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) {
 		return;
 	}
-		
-	/* Add a Gart apeture resource */
-	if (dev->resources < MAX_RESOURCES) {
-		resource = &dev->resource[dev->resources];
-		dev->resources++;
-		resource->base  = 0;
-		resource->size  = AGP_APERTURE_SIZE;
+
+	iommu = 1;
+	get_option(&iommu, "iommu");
+
+	if (iommu) {
+		/* Add a Gart apeture resource */
+		resource = new_resource(dev, 0x94);
+		resource->size = iommu?AGP_APERTURE_SIZE:1;
 		resource->align = log2(resource->size);
 		resource->gran  = log2(resource->size);
 		resource->limit = 0xffffffff; /* 4G */
 		resource->flags = IORESOURCE_MEM;
-		resource->index = 0x94;
-	} else {
-		printk_err("%s Unexpeted resource shortage\n", dev_path(dev));
 	}
 }
 
-static void set_agp_aperture(device_t dev, struct resource *resource)
+static void set_agp_aperture(device_t dev)
 {
-	device_t pdev;
-	uint32_t base;
-	uint32_t size;
+	struct resource *resource;
 		
-	size = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0);
-	base = ((resource->base) >> 25) & 0x00007fff;
-	pdev = 0;
-
-	/* A search for MISC Control device is neceressary */
-	while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
-		pci_write_config32(pdev, 0x90, size);
-		pci_write_config32(pdev, 0x94, base);
-		/* Don't set the GART Table base address */
-		pci_write_config32(pdev, 0x98, 0);
-
-		printk_debug("%s %02x <- [0x%08lx - 0x%08lx] mem <gart>\n",
-			     dev_path(pdev), resource->index, resource->base,
-			     resource->base + resource->size - 1);
+	resource = probe_resource(dev, 0x94);
+	if (resource) {
+		device_t pdev;
+		uint32_t gart_base, gart_acr;
+		/* Remember this resource has been stored */
+		resource->flags |= IORESOURCE_STORED;
+
+		/*Find the size of the GART aperture */
+		gart_acr  = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0);
+
+		/* Get the base address */
+		gart_base = ((resource->base) >> 25) & 0x00007fff;
+		
+		/* Update the other northbriges */
+		pdev = 0;
+		while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
+			/* Store GART size but don't enable it */
+			pci_write_config32(pdev, 0x90, gart_acr);
+
+			/* Store the GART base address */
+			pci_write_config32(pdev, 0x94, gart_base);
+
+			/* Don't set the GART Table base address */
+			pci_write_config32(pdev, 0x98, 0);
+			
+			/* Report the resource has been stored... */
+			report_resource_stored(pdev, resource, " <gart>");
+		}
 	}
-	/* Remember this resource has been stored */
-	resource->flags |= IORESOURCE_STORED;	
 }
 
 static void mcf3_set_resources(device_t dev)
 {
-	struct resource *resource, *last;
-
-	last = &dev->resource[dev->resources];
-	for (resource = &dev->resource[0]; resource < last; resource++) {
-		if (resource->index == 0x94) {
-			set_agp_aperture(dev, resource);
-		}
-	}
+	/* Set the gart apeture */
+	set_agp_aperture(dev);
 
 	/* Set the generic PCI resources */
 	pci_dev_set_resources(dev);