diff options
Diffstat (limited to 'src/northbridge/amd/amdfam10')
| -rw-r--r-- | src/northbridge/amd/amdfam10/amdfam10.h | 6 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/conf.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/debug.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/early_ht.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 54 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/reset_test.c | 2 |
6 files changed, 39 insertions, 39 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 99518065de..712c98638e 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -976,7 +976,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT //struct definitions @@ -1034,7 +1034,7 @@ struct nodes_info_t { } __attribute__((packed)); /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/ -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT //#define MEM_CS_COPY 1 #define MEM_CS_COPY NODE_NUMS @@ -1102,7 +1102,7 @@ struct sys_info { device_t get_node_pci(u32 nodeid, u32 fn); #endif -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT #ifdef __PRE_RAM__ static void soft_reset(void); diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c index adfff0f6e3..d8c161fc3d 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/conf.c @@ -38,7 +38,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) dev = __f1_dev[0]; #endif -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // I will use ext space only for simple pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 @@ -61,12 +61,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) { u32 i; device_t dev; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // I will use ext space only for simple u32 d_base_i, d_base_d, d_mask_i, d_mask_d; d_base_i = nodeid | (0<<28); @@ -95,7 +95,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) dev = __f1_dev[i]; #endif -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // I will use ext space only for simple pci_write_config32(dev, 0x110, d_base_i); pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8]; @@ -120,7 +120,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) } #endif -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 2dc54275fd..c6f7c780a9 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -33,7 +33,7 @@ static inline void print_debug_addr(const char *str, void *val) static void print_debug_pci_dev(u32 dev) { -#if CONFIG_PCI_BUS_SEGN_BITS==0 +#if !CONFIG_PCI_BUS_SEGN_BITS printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); #else printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 58f2cddb36..bbf6b86ac9 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -21,7 +21,7 @@ // mmconf is not ready yet static void set_bsp_node_CHtExtNodeCfgEn(void) { -#if CONFIG_EXT_RT_TBL_SUPPORT == 1 +#if CONFIG_EXT_RT_TBL_SUPPORT u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); @@ -112,7 +112,7 @@ static void enumerate_ht_chain(void) real_last_pos = pos; ht_dev_num++ ; #endif - #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0 + #if !CONFIG_HT_CHAIN_END_UNITID_BASE if (!next_unitid) goto out; #endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 89bd6733ce..0e80c71324 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/lapic.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #include <pc80/mc146818rtc.h> #endif @@ -161,7 +161,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l #endif u32 max_devfn; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT if(is_sublink1) { u32 regpos; u32 reg; @@ -192,7 +192,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l */ ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf); -#if CONFIG_EXT_CONF_SUPPORT == 0 +#if !CONFIG_EXT_CONF_SUPPORT if(ht_c_index>=4) return max; #endif @@ -316,7 +316,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; @@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } @@ -460,7 +460,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -477,7 +477,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -664,7 +664,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); #else struct bus *link; @@ -762,7 +762,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) // WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards. // Does it make sense not to? -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; @@ -843,11 +843,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #endif -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -865,7 +865,7 @@ static void add_uma_resource(struct device *dev, int index) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -878,7 +878,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM for(link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the @@ -960,7 +960,7 @@ static void amdfam10_domain_set_resources(device_t dev) reset_memhole = 0; } - #if CONFIG_AMDMCT == 0 + #if !CONFIG_AMDMCT //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { @@ -975,7 +975,7 @@ static void amdfam10_domain_set_resources(device_t dev) disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC // We need to double check if the mmio_basek is valid for hole // setting, if it is equal to basek, we need to decrease it some resource_t basek_pri; @@ -1031,10 +1031,10 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -1045,7 +1045,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #endif } - #if CONFIG_AMDMCT == 0 + #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) { struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM @@ -1067,19 +1067,19 @@ static void amdfam10_domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA /* Deduct uma memory before reporting because * this is what the mtrr code expects */ sizek -= uma_memory_size / 1024; #endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; @@ -1089,7 +1089,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA add_uma_resource(dev, 7); #endif @@ -1109,7 +1109,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // all nodes for(i = 0; i< sysconf.nodes; i++) { int index; @@ -1187,7 +1187,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; @@ -1265,7 +1265,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS get_option(&disable_siblings, "multi_core"); #endif @@ -1371,7 +1371,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * otherwise the device under it will not be scanned */ int linknum; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT linknum = 8; #else linknum = 4; diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index c48fca630c..f1f22cbf35 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -127,7 +127,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b } } -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // let's check that in extend space // use the nodeid extend space to find out the bus for the linkn u32 tempreg; |