diff options
Diffstat (limited to 'src/northbridge/amd/amdfam10')
32 files changed, 0 insertions, 7325 deletions
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig deleted file mode 100644 index 64358875f1..0000000000 --- a/src/northbridge/amd/amdfam10/Kconfig +++ /dev/null @@ -1,145 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config NORTHBRIDGE_AMD_AMDFAM10 - bool - select HAVE_DEBUG_RAM_SETUP - select HAVE_DEBUG_SMBUS - select HAVE_DEBUG_CAR - select HYPERTRANSPORT_PLUGIN_SUPPORT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE - select NO_RELOCATABLE_RAMSTAGE - -if NORTHBRIDGE_AMD_AMDFAM10 -config AGP_APERTURE_SIZE - hex - default 0x4000000 - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MMCONF_BASE_ADDRESS - hex - default 0xc0000000 - -config MMCONF_BUS_NUMBER - int - default 256 - -# TODO: Reservation for heap seems excessive -config HEAP_SIZE - hex - default 0xc0000 - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" - -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - -config HT_CHAIN_DISTRIBUTE - def_bool n - -config DIMM_DDR2 - bool - default n - -config DIMM_DDR3 - bool - default n - -config DIMM_REGISTERED - bool - default n - -config DIMM_VOLTAGE_SET_SUPPORT - bool - default n - -config S3_DATA_SIZE - int - default 32768 - depends on (HAVE_ACPI_RESUME) - -config S3_DATA_POS - hex - default 0x0 - depends on (HAVE_ACPI_RESUME) - -config SVI_HIGH_FREQ - bool - default n - help - Select this for boards with a Voltage Regulator able to operate - at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. - -menu "HyperTransport setup" - #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -endmenu - -config MAX_REBOOT_CNT - int - default 6 - -endif # NORTHBRIDGE_AMD_AMDFAM10 diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc deleted file mode 100644 index 787f4444ce..0000000000 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) - -subdirs-y += ../amdht -subdirs-y += ../amdmct/wrappers -subdirs-$(CONFIG_DIMM_DDR3) += ../amdmct/mct_ddr3 -subdirs-$(CONFIG_DIMM_DDR2) += ../amdmct/mct - -# Generic ROMSTAGE stuff -romstage-y += reset_test.c debug.c setup_resource_map.c raminit_sysinfo_in_ram.c -romstage-y += raminit_amdmct.c pci.c early_ht.c amdfam10_util.c - -# RAMSTAGE -ramstage-y += northbridge.c misc_control.c link_control.c nb_control.c -ramstage-y += amdfam10_util.c ht_config.c get_pci1234.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c - -# Enable this if you want to check the values of the PCI routing registers. -# Call show_all_routes() anywhere amdfam10.h is included. -#ramstage-y += util.c - -# Reserve 2x CONFIG_S3_DATA_SIZE to allow for random file placement -# (not respecting erase sector boundaries) within CBFS -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1*2; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-$(CONFIG_HAVE_ACPI_RESUME) += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-align := $(CONFIG_S3_DATA_SIZE) -s3nv-type := raw - -endif diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c deleted file mode 100644 index dc139adb87..0000000000 --- a/src/northbridge/amd/amdfam10/acpi.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <device/pci.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam10_sysconf.h> -#include "amdfam10.h" - -//it seems some functions can be moved arch/x86/boot/acpi.c - -unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); - cpu_index++; - } - return current; -} - -unsigned long acpi_create_srat_lapics(unsigned long current) -{ - struct device *cpu; - int cpu_index = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - -static unsigned long resk(uint64_t value) -{ - unsigned long resultk; - if (value < (1ULL << 42)) { - resultk = value >> 10; - } else { - resultk = 0xffffffff; - } - return resultk; -} - -struct acpi_srat_mem_state { - unsigned long current; -}; - -static void set_srat_mem(void *gp, struct device *dev, struct resource *res) -{ - struct acpi_srat_mem_state *state = gp; - unsigned long basek, sizek; - basek = resk(res->base); - sizek = resk(res->size); - - printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n", - dev_path(dev), res->index, basek, sizek); - /* - * 0-640K must be on node 0 - * next range is from 1M--- - * So will cut off before 1M in the mem range - */ - if ((basek+sizek)<1024) return; - - if (basek < 1024) { - sizek -= 1024 - basek; - basek = 1024; - } - - // need to figure out NV - if (res->index > 0xf) /* Exclude MMIO resources, e.g. as set in northbridge.c amdfam10_domain_read_resources() */ - state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); -} - -static unsigned long acpi_fill_srat(unsigned long current) -{ - struct acpi_srat_mem_state srat_mem_state; - - /* create all subtables for processors */ - current = acpi_create_srat_lapics(current); - - /* create all subteble for memory range */ - - /* 0-640K must be on node 0 */ - current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable - - srat_mem_state.current = current; - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - set_srat_mem, &srat_mem_state); - - current = srat_mem_state.current; - return current; -} - -static unsigned long acpi_fill_slit(unsigned long current) -{ - /* Implement SLIT algorithm in BKDG Rev. 3.62 Section 2.3.6.1 - * Fill the first 8 bytes with the node number, - * then fill the next num*num byte with the distance, - * Distance entries vary with topology; the local node - * is always 10. - * - * Fully connected: - * Set all non-local nodes to 16 - * - * Partially connected; with probe filter: - * Set all non-local nodes to 10+(num_hops*6) - * - * Partially connected; without probe filter: - * Set all non-local nodes to 13 - * - * FIXME - * The partially connected cases are not implemented; - * once a means is found to detect partially connected - * topologies, implement the remaining cases. - */ - - u8 *p = (u8 *)current; - int nodes = sysconf.nodes; - int i,j; - - memset(p, 0, 8+nodes*nodes); - *p = (u8) nodes; - p += 8; - - for (i = 0; i < nodes; i++) { - for (j = 0; j < nodes; j++) { - if (i == j) - p[i*nodes+j] = 10; - else - p[i*nodes+j] = 16; - } - } - - current += 8+nodes*nodes; - return current; -} - -void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (u8) ('4' + i - 1); - } else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - -void northbridge_acpi_write_vars(struct device *device) -{ - /* - * If more than one physical CPU is installed, northbridge_acpi_write_vars() - * is called more than once and the resultant SSDT table is corrupted - * (duplicated entries). - * This prevents Linux from booting, with log messages like these: - * ACPI Error: [BUSN] Namespace lookup failure, AE_ALREADY_EXISTS (/dswload-353) - * ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (/psobject-222) - * followed by a slew of ACPI method failures and a hang when the invalid PCI - * resource entries are used. - * This routine prevents the SSDT table from being corrupted. - */ - static uint8_t ssdt_generated = 0; - if (ssdt_generated) - return; - ssdt_generated = 1; - - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - int i; - - acpigen_write_scope(pscope); - - acpigen_write_name("BUSN"); - acpigen_write_package(HC_NUMS); - for (i = 0; i < HC_NUMS; i++) { - acpigen_write_dword(sysconf.ht_c_conf_bus[i]); - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name("MMIO"); - - acpigen_write_package(HC_NUMS * 4); - - for (i = 0; i<(HC_NUMS*2); i++) { // FIXME: change to more chain - acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base - acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name("PCIO"); - - acpigen_write_package(HC_NUMS * 2); - - for (i = 0; i < HC_NUMS; i++) { // FIXME: change to more chain - acpigen_write_dword(sysconf.conf_io_addrx[i]); - acpigen_write_dword(sysconf.conf_io_addr[i]); - } - - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name_byte("SBLK", sysconf.sblk); - - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - - - acpigen_write_name_dword("SBDN", sysconf.sbdn); - - acpigen_write_name("HCLK"); - - acpigen_write_package(HC_POSSIBLE_NUM); - - for (i = 0; i < sysconf.hc_possible_num; i++) { - acpigen_write_dword(sysconf.pci1234[i]); - } - for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 - acpigen_write_dword(0x00000000); - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name("HCDN"); - - acpigen_write_package(HC_POSSIBLE_NUM); - - for (i = 0; i < sysconf.hc_possible_num; i++) { - acpigen_write_dword(sysconf.hcdn[i]); - } - for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 - acpigen_write_dword(0x20202020); - } - // minus the opcode - acpigen_pop_len(); - - acpigen_write_name_byte("CBB", CONFIG_CBB); - - u8 CBST, CBB2, CBS2; - - if (CONFIG_CBB == 0xff) { - CBST = (u8) (0x0f); - } else { - if ((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 - CBST = (u8) (0x0f); - } else { - CBST = (u8) (0x00); - } - } - - acpigen_write_name_byte("CBST", CBST); - - if ((CONFIG_CBB == 0xff) && (sysconf.nodes > 32)) { - CBS2 = 0x0f; - CBB2 = (u8)(CONFIG_CBB-1); - } else { - CBS2 = 0x00; - CBB2 = 0x00; - } - - acpigen_write_name_byte("CBB2", CBB2); - acpigen_write_name_byte("CBS2", CBS2); - - //minus opcode - acpigen_pop_len(); -} - -unsigned long northbridge_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - - return current; -} diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h deleted file mode 100644 index ad8d01365d..0000000000 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ /dev/null @@ -1,1025 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_H -#define AMDFAM10_H - -#include <stdint.h> -#include <device/device.h> -#include "early_ht.h" - -#include "inline_helper.c" -struct DCTStatStruc; -struct MCTStatStruc; - - -/* Definitions for setup_resourcemap() variants. */ - -#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) - -#define ADDRMAP_REG(r) PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, r) - -#define RES_PCI_IO 0x10 -#define RES_PORT_IO_8 0x22 -#define RES_PORT_IO_32 0x20 -#define RES_MEM_IO 0x40 - -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) - -/* Definitions of various FAM10 registers */ -/* Function 0 */ -#define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) -#define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) -#define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) -#define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 -#define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 - - -/* Function 1 */ -#define PCI_IO_BASE0 0xc0 -#define PCI_IO_BASE1 0xc8 -#define PCI_IO_BASE2 0xd0 -#define PCI_IO_BASE3 0xd8 -#define PCI_IO_BASE_VGA_EN (1 << 4) -#define PCI_IO_BASE_NO_ISA (1 << 5) - -/* Function 2 */ -// 0x1xx is for DCT1 -#define DRAM_CSBASE 0x40 -#define DRAM_CSMASK 0x60 -#define DRAM_BANK_ADDR_MAP 0x80 - -#define DRAM_CTRL 0x78 -#define DC_RdPtrInit_SHIFT 0 -#define DC_RdPrtInit_MASK 0xf -#define DC_Twrrd3_2_SHIFT 8 /*DDR3 */ -#define DC_Twrrd3_2_MASK 3 -#define DC_Twrwr3_2_SHIFT 10 /*DDR3 */ -#define DC_Twrwr3_2_MASK 3 -#define DC_Trdrd3_2_SHIFT 12 /*DDR3 */ -#define DC_Trdrd3_2_MASK 3 -#define DC_AltVidC3MemClkTriEn (1<<16) -#define DC_DqsRcvEnTrain (1<<18) -#define DC_MaxRdLatency_SHIFT 22 -#define DC_MaxRdLatency_MASK 0x3ff - -#define DRAM_INIT 0x7c -#define DI_MrsAddress_SHIFT 0 -#define DI_MrsAddress_MASK 0xffff -#define DI_MrsBank_SHIFT 16 -#define DI_MrsBank_MASK 7 -#define DI_MrsChipSel_SHIFT 20 -#define DI_MrsChipSel_MASK 7 -#define DI_SendRchgAll (1<<24) -#define DI_SendAutoRefresh (1<<25) -#define DI_SendMrsCmd (1<<26) -#define DI_DeassertMemRstX (1<<27) -#define DI_AssertCke (1<<28) -#define DI_SendZQCmd (1<<29) /*DDR3 */ -#define DI_EnMrsCmd (1<<30) -#define DI_EnDramInit (1<<31) - -#define DRAM_MRS 0x84 -#define DM_BurstCtrl_SHIFT 0 -#define DM_BurstCtrl_MASK 3 -#define DM_DrvImpCtrl_SHIFT 2 /* DDR3 */ -#define DM_DrvImpCtrl_MASK 3 -#define DM_Twr_SHIFT 4 /* DDR3 */ -#define DM_Twr_MASK 7 -#define DM_Twr_BASE 4 -#define DM_Twr_MIN 5 -#define DM_Twr_MAX 12 -#define DM_DramTerm_SHIFT 7 /*DDR3 */ -#define DM_DramTerm_MASK 7 -#define DM_DramTermDyn_SHIFT 10 /* DDR3 */ -#define DM_DramTermDyn_MASK 3 -#define DM_Ooff (1<<13) -#define DM_ASR (1<<18) -#define DM_SRT (1<<19) -#define DM_Tcwl_SHIFT 20 -#define DM_Tcwl_MASK 7 -#define DM_PchgPDModeSel (1<<23) /* DDR3 */ -#define DM_MPrLoc_SHIFT 24 /* DDR3 */ -#define DM_MPrLoc_MASK 3 -#define DM_MprEn (1<<26) /* DDR3 */ - -#define DRAM_TIMING_LOW 0x88 -#define DTL_TCL_SHIFT 0 -#define DTL_TCL_MASK 0xf -#define DTL_TCL_BASE 1 /* DDR3 =4 */ -#define DTL_TCL_MIN 3 /* DDR3 =4 */ -#define DTL_TCL_MAX 6 /* DDR3 =12 */ -#define DTL_TRCD_SHIFT 4 -#define DTL_TRCD_MASK 3 /* DDR3 =7 */ -#define DTL_TRCD_BASE 3 /* DDR3 =5 */ -#define DTL_TRCD_MIN 3 /* DDR3 =5 */ -#define DTL_TRCD_MAX 6 /* DDR3 =12 */ -#define DTL_TRP_SHIFT 8 /* DDR3 =7 */ -#define DTL_TRP_MASK 3 /* DDR3 =7 */ -#define DTL_TRP_BASE 3 /* DDR3 =5 */ -#define DTL_TRP_MIN 3 /* DDR3 =5 */ -#define DTL_TRP_MAX 6 /* DDR3 =12 */ -#define DTL_TRTP_SHIFT 11 /*DDR3 =10 */ -#define DTL_TRTP_MASK 1 /*DDR3 =3 */ -#define DTL_TRTP_BASE 2 /* DDR3 =4 */ -#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */ -#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */ -#define DTL_TRAS_SHIFT 12 -#define DTL_TRAS_MASK 0xf -#define DTL_TRAS_BASE 3 /* DDR3 =15 */ -#define DTL_TRAS_MIN 5 /* DDR3 =15 */ -#define DTL_TRAS_MAX 18 /*DDR3 =30 */ -#define DTL_TRC_SHIFT 16 -#define DTL_TRC_MASK 0xf /* DDR3 =0x1f */ -#define DTL_TRC_BASE 11 -#define DTL_TRC_MIN 11 -#define DTL_TRC_MAX 26 /* DDR3 =43 */ -#define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */ -#define DTL_TWR_MASK 3 -#define DTL_TWR_BASE 3 -#define DTL_TWR_MIN 3 -#define DTL_TWR_MAX 6 -#define DTL_TRRD_SHIFT 22 -#define DTL_TRRD_MASK 3 -#define DTL_TRRD_BASE 2 /* DDR3 =4 */ -#define DTL_TRRD_MIN 2 /* DDR3 =4 */ -#define DTL_TRRD_MAX 5 /* DDR3 =7 */ -#define DTL_MemClkDis_SHIFT 24 /* Channel A */ -#define DTL_MemClkDis3 (1 << 26) -#define DTL_MemClkDis2 (1 << 27) -#define DTL_MemClkDis1 (1 << 28) -#define DTL_MemClkDis0 (1 << 29) -/* DTL_MemClkDis for m2 and s1g1 is different */ - -#define DRAM_TIMING_HIGH 0x8c -#define DTH_TRWTWB_SHIFT 0 -#define DTH_TRWTWB_MASK 3 -#define DTH_TRWTWB_BASE 3 /* DDR3 =4 */ -#define DTH_TRWTWB_MIN 3 /* DDR3 =5 */ -#define DTH_TRWTWB_MAX 10 /* DDR3 =11 */ -#define DTH_TRWTTO_SHIFT 4 -#define DTH_TRWTTO_MASK 7 -#define DTH_TRWTTO_BASE 2 /* DDR3 =3 */ -#define DTH_TRWTTO_MIN 2 /* DDR3 =3 */ -#define DTH_TRWTTO_MAX 9 /* DDR3 =10 */ -#define DTH_TWTR_SHIFT 8 -#define DTH_TWTR_MASK 3 -#define DTH_TWTR_BASE 0 /* DDR3 =4 */ -#define DTH_TWTR_MIN 1 /* DDR3 =4 */ -#define DTH_TWTR_MAX 3 /* DDR3 =7 */ -#define DTH_TWRRD_SHIFT 10 -#define DTH_TWRRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TWRRD_BASE 0 /* DDR3 =0 */ -#define DTH_TWRRD_MIN 0 /* DDR3 =2 */ -#define DTH_TWRRD_MAX 3 /* DDR3 =12 */ -#define DTH_TWRWR_SHIFT 12 -#define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TWRWR_BASE 1 -#define DTH_TWRWR_MIN 1 /* DDR3 =3 */ -#define DTH_TWRWR_MAX 3 /* DDR3 =12 */ -#define DTH_TRDRD_SHIFT 14 -#define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TRDRD_BASE 2 -#define DTH_TRDRD_MIN 2 -#define DTH_TRDRD_MAX 5 /* DDR3 =10 */ -#define DTH_TREF_SHIFT 16 -#define DTH_TREF_MASK 3 -#define DTH_TREF_7_8_US 2 -#define DTH_TREF_3_9_US 3 -#define DTH_DisAutoRefresh (1<<18) -#define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ -#define DTH_TRFC_MASK 7 -#define DTH_TRFC_75_256M 0 -#define DTH_TRFC_105_512M 1 -#define DTH_TRFC_127_5_1G 2 -#define DTH_TRFC_195_2G 3 -#define DTH_TRFC_327_5_4G 4 -#define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ -#define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ -#define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ - -#define DRAM_CONFIG_LOW 0x90 -#define DCL_InitDram (1<<0) -#define DCL_ExitSelfRef (1<<1) -#define DCL_PllLockTime_SHIFT 2 -#define DCL_PllLockTime_MASK 3 -#define DCL_PllLockTime_15US 0 -#define DCL_PllLockTime_6US 1 -#define DCL_DramTerm_SHIFT 4 -#define DCL_DramTerm_MASK 3 -#define DCL_DramTerm_No 0 -#define DCL_DramTerm_75_OH 1 -#define DCL_DramTerm_150_OH 2 -#define DCL_DramTerm_50_OH 3 -#define DCL_DisDqsBar (1<<6) /* only for DDR2 */ -#define DCL_DramDrvWeak (1<<7) /* only for DDR2 */ -#define DCL_ParEn (1<<8) -#define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */ -#define DCL_BurstLength32 (1<<10) /* only for DDR3 */ -#define DCL_Width128 (1<<11) -#define DCL_X4Dimm_SHIFT 12 -#define DCL_X4Dimm_MASK 0xf -#define DCL_UnBuffDimm (1<<16) -#define DCL_EnPhyDqsRcvEnTr (1<<18) -#define DCL_DimmEccEn (1<<19) -#define DCL_DynPageCloseEn (1<<20) -#define DCL_IdleCycInit_SHIFT 21 -#define DCL_IdleCycInit_MASK 3 -#define DCL_IdleCycInit_16CLK 0 -#define DCL_IdleCycInit_32CLK 1 -#define DCL_IdleCycInit_64CLK 2 -#define DCL_IdleCycInit_96CLK 3 -#define DCL_ForceAutoPchg (1<<23) - -#define DRAM_CONFIG_HIGH 0x94 -#define DCH_MemClkFreq_SHIFT 0 -#define DCH_MemClkFreq_MASK 7 -#define DCH_MemClkFreq_200MHz 0 /* DDR2 */ -#define DCH_MemClkFreq_266MHz 1 /* DDR2 */ -#define DCH_MemClkFreq_333MHz 2 /* DDR2 */ -#define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/ -#define DCH_MemClkFreq_533MHz 4 /* DDR 3 */ -#define DCH_MemClkFreq_667MHz 5 /* DDR 3 */ -#define DCH_MemClkFreq_800MHz 6 /* DDR 3 */ -#define DCH_MemClkFreqVal (1<<3) -#define DCH_Ddr3Mode (1<<8) -#define DCH_LegacyBiosMode (1<<9) -#define DCH_ZqcsInterval_SHIFT 10 -#define DCH_ZqcsInterval_MASK 3 -#define DCH_ZqcsInterval_DIS 0 -#define DCH_ZqcsInterval_64MS 1 -#define DCH_ZqcsInterval_128MS 2 -#define DCH_ZqcsInterval_256MS 3 -#define DCH_RDqsEn (1<<12) /* only for DDR2 */ -#define DCH_DisSimulRdWr (1<<13) -#define DCH_DisDramInterface (1<<14) -#define DCH_PowerDownEn (1<<15) -#define DCH_PowerDownMode_SHIFT 16 -#define DCH_PowerDownMode_MASK 1 -#define DCH_PowerDownMode_Channel_CKE 0 -#define DCH_PowerDownMode_ChipSelect_CKE 1 -#define DCH_FourRankSODimm (1<<17) -#define DCH_FourRankRDimm (1<<18) -#define DCH_SlowAccessMode (1<<20) -#define DCH_BankSwizzleMode (1<<22) -#define DCH_DcqBypassMax_SHIFT 24 -#define DCH_DcqBypassMax_MASK 0xf -#define DCH_DcqBypassMax_BASE 0 -#define DCH_DcqBypassMax_MIN 0 -#define DCH_DcqBypassMax_MAX 15 -#define DCH_FourActWindow_SHIFT 28 -#define DCH_FourActWindow_MASK 0xf -#define DCH_FourActWindow_BASE 7 /* DDR3 15 */ -#define DCH_FourActWindow_MIN 8 /* DDR3 16 */ -#define DCH_FourActWindow_MAX 20 /* DDR3 30 */ - - -// for 0x98 index and 0x9c data for DCT0 -// for 0x198 index and 0x19c data for DCT1 -// even at ganged mode, 0x198/0x19c will be used for channel B - -#define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 -#define DCAO_DctOffset_SHIFT 0 -#define DCAO_DctOffset_MASK 0x3fffffff -#define DCAO_DctAccessWrite (1<<30) -#define DCAO_DctAccessDone (1<<31) - -#define DRAM_CTRL_ADDI_DATA_PORT 0x9c - -#define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 -#define DODCC_CkeDrvStren_SHIFT 0 -#define DODCC_CkeDrvStren_MASK 3 -#define DODCC_CkeDrvStren_1_0X 0 -#define DODCC_CkeDrvStren_1_25X 1 -#define DODCC_CkeDrvStren_1_5X 2 -#define DODCC_CkeDrvStren_2_0X 3 -#define DODCC_CsOdtDrvStren_SHIFT 4 -#define DODCC_CsOdtDrvStren_MASK 3 -#define DODCC_CsOdtDrvStren_1_0X 0 -#define DODCC_CsOdtDrvStren_1_25X 1 -#define DODCC_CsOdtDrvStren_1_5X 2 -#define DODCC_CsOdtDrvStren_2_0X 3 -#define DODCC_AddrCmdDrvStren_SHIFT 8 -#define DODCC_AddrCmdDrvStren_MASK 3 -#define DODCC_AddrCmdDrvStren_1_0X 0 -#define DODCC_AddrCmdDrvStren_1_25X 1 -#define DODCC_AddrCmdDrvStren_1_5X 2 -#define DODCC_AddrCmdDrvStren_2_0X 3 -#define DODCC_ClkDrvStren_SHIFT 12 -#define DODCC_ClkDrvStren_MASK 3 -#define DODCC_ClkDrvStren_0_75X 0 -#define DODCC_ClkDrvStren_1_0X 1 -#define DODCC_ClkDrvStren_1_25X 2 -#define DODCC_ClkDrvStren_1_5X 3 -#define DODCC_DataDrvStren_SHIFT 16 -#define DODCC_DataDrvStren_MASK 3 -#define DODCC_DataDrvStren_0_75X 0 -#define DODCC_DataDrvStren_1_0X 1 -#define DODCC_DataDrvStren_1_25X 2 -#define DODCC_DataDrvStren_1_5X 3 -#define DODCC_DqsDrvStren_SHIFT 20 -#define DODCC_DqsDrvStren_MASK 3 -#define DODCC_DqsDrvStren_0_75X 0 -#define DODCC_DqsDrvStren_1_0X 1 -#define DODCC_DqsDrvStren_1_25X 2 -#define DODCC_DqsDrvStren_1_5X 3 -#define DODCC_ProcOdt_SHIFT 28 -#define DODCC_ProcOdt_MASK 3 -#define DODCC_ProcOdt_300_OHMS 0 -#define DODCC_ProcOdt_150_OHMS 1 -#define DODCC_ProcOdt_75_OHMS 2 - -/* - for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs - for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 - So Socket F with Four Logical DIMM will only support DDR2 800 ? -*/ -/* there are index +100 ===> for DIMM1 -that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 -*/ -//02/15/2006 18:37 -#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 -#define DWDTC_WrDatFineDlyByte0_SHIFT 0 -#define DWDTC_WrDatFineDlyByte_MASK 0x1f -#define DWDTC_WrDatFineDlyByte_BASE 0 -#define DWDTC_WrDatFineDlyByte_MIN 0 -#define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK -#define DWDTC_WrDatGrossDlyByte0_SHIFT 5 -#define DWDTC_WrDatGrossDlyByte_MASK 0x3 -#define DWDTC_WrDatGrossDlyByte_NO_DELAY 0 -#define DWDTC_WrDatGrossDlyByte_0_5_ 1 -#define DWDTC_WrDatGrossDlyByte_1 2 -#define DWDTC_WrDatFineDlyByte1_SHIFT 8 -#define DWDTC_WrDatGrossDlyByte1_SHIFT 13 -#define DWDTC_WrDatFineDlyByte2_SHIFT 16 -#define DWDTC_WrDatGrossDlyByte2_SHIFT 21 -#define DWDTC_WrDatFineDlyByte3_SHIFT 24 -#define DWDTC_WrDatGrossDlyByte3_SHIFT 29 - -#define DRAM_WRITE_DATA_TIMING_CTRL_HIGH 0x02 -#define DWDTC_WrDatFineDlyByte4_SHIFT 0 -#define DWDTC_WrDatGrossDlyByte4_SHIFT 5 -#define DWDTC_WrDatFineDlyByte5_SHIFT 8 -#define DWDTC_WrDatGrossDlyByte5_SHIFT 13 -#define DWDTC_WrDatFineDlyByte6_SHIFT 16 -#define DWDTC_WrDatGrossDlyByte6_SHIFT 21 -#define DWDTC_WrDatFineDlyByte7_SHIFT 24 -#define DWDTC_WrDatGrossDlyByte7_SHIFT 29 - -#define DRAM_WRITE_ECC_TIMING_CTRL 0x03 -#define DWETC_WrChkFinDly_SHIFT 0 -#define DWETC_WrChkGrossDly_SHIFT 5 - -#define DRAM_ADDR_CMD_TIMING_CTRL 0x04 -#define DACTC_CkeFineDelay_SHIFT 0 -#define DACTC_CkeFineDelay_MASK 0x1f -#define DACTC_CkeFineDelay_BASE 0 -#define DACTC_CkeFineDelay_MIN 0 -#define DACTC_CkeFineDelay_MAX 31 -#define DACTC_CkeSetup (1<<5) -#define DACTC_CsOdtFineDelay_SHIFT 8 -#define DACTC_CsOdtFineDelay_MASK 0x1f -#define DACTC_CsOdtFineDelay_BASE 0 -#define DACTC_CsOdtFineDelay_MIN 0 -#define DACTC_CsOdtFineDelay_MAX 31 -#define DACTC_CsOdtSetup (1<<13) -#define DACTC_AddrCmdFineDelay_SHIFT 16 -#define DACTC_AddrCmdFineDelay_MASK 0x1f -#define DACTC_AddrCmdFineDelay_BASE 0 -#define DACTC_AddrCmdFineDelay_MIN 0 -#define DACTC_AddrCmdFineDelay_MAX 31 -#define DACTC_AddrCmdSetup (1<<21) - -#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 -#define DRDTC_RdDqsTimeByte0_SHIFT 0 -#define DRDTC_RdDqsTimeByte_MASK 0x3f -#define DRDTC_RdDqsTimeByte_BASE 0 -#define DRDTC_RdDqsTimeByte_MIN 0 -#define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK -#define DRDTC_RdDqsTimeByte1_SHIFT 8 -#define DRDTC_RdDqsTimeByte2_SHIFT 16 -#define DRDTC_RdDqsTimeByte3_SHIFT 24 - -#define DRAM_READ_DQS_TIMING_CTRL_HIGH 0x06 -#define DRDTC_RdDqsTimeByte4_SHIFT 0 -#define DRDTC_RdDqsTimeByte5_SHIFT 8 -#define DRDTC_RdDqsTimeByte6_SHIFT 16 -#define DRDTC_RdDqsTimeByte7_SHIFT 24 - -#define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07 -#define DRDETC_RdDqsTimeCheck_SHIFT 0 - -#define DRAM_PHY_CTRL 0x08 -#define DPC_WrtLvTrEn (1<<0) -#define DPC_WrtLvTrMode (1<<1) -#define DPC_TrNibbleSel (1<<2) -#define DPC_TrDimmSel_SHIFT 4 -#define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */ -#define DPC_WrLvOdt_SHIFT 8 -#define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/ -#define DPC_WrLvODtEn (1<<12) -#define DPC_DqsRcvTrEn (1<<13) -#define DPC_DisAutoComp (1<<30) -#define DPC_AsyncCompUpdate (1<<31) - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A -#define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0 -#define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f -#define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5 -#define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3 -#define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte2_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte3_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte3_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_1 0x11 //DIMM0 Channel A -#define DDRETC_DqsRcvEnFineDelayByte4_SHIFT 0 -#define DDRETC_DqsRcvEnGrossDelayByte4_SHIFT 5 -#define DDRETC_DqsRcvEnFineDelayByte5_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte5_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte6_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte6_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte7_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte7_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_0 0x12 -#define DDRETCE_WrChkFineDlyByte0_SHIFT 0 -#define DDRETCE_WrChkGrossDlyByte0_SHIFT 5 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B -#define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0 -#define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5 -#define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte9_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte10_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte10_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte11_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte11_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_3 0x21 // DIMM0 Channel B -#define DDRETC_DqsRcvEnFineDelayByte12_SHIFT 0 -#define DDRETC_DqsRcvEnGrossDelayByte12_SHIFT 5 -#define DDRETC_DqsRcvEnFineDelayByte13_SHIFT 8 -#define DDRETC_DqsRcvEnGrossDelayByte13_SHIFT 13 -#define DDRETC_DqsRcvEnFineDelayByte14_SHIFT 16 -#define DDRETC_DqsRcvEnGrossDelayByte14_SHIFT 21 -#define DDRETC_DqsRcvEnFineDelayByte15_SHIFT 24 -#define DDRETC_DqsRcvEnGrossDelayByte15_SHIFT 29 - -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_0_1 0x22 -#define DDRETCE_WrChkFineDlyByte1_SHIFT 0 -#define DDRETCE_WrChkGrossDlyByte1_SHIFT 5 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_0 0x13 //DIMM1 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_1 0x14 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_0 0x15 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_2 0x23 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_3 0x24 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_1 0x25 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_1 0x17 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_0 0x18 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_2 0x26 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_3 0x27 -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_1 0x28 - -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_1 0x1a -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_0 0x1b -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_2 0x29 -#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_3 0x2a -#define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_1 0x2b - -/* 04.06.2006 19:12 */ - -#define DRAM_PHASE_RECOVERY_CTRL_0 0x50 -#define DPRC_PhRecFineDlyByte0_SHIFT 0 -#define DDWTC_PhRecFineDlyByte0_MASK 0x1f -#define DDWTC_PhRecGrossDlyByte0_SHIFT 5 -#define DDWTC_PhRecGrossDlyByte0_MASK 0x3 -#define DDWTC_PhRecFineDlyByte1_SHIFT 8 -#define DDWTC_PhRecGrossDlyByte1_SHIFT 13 -#define DDWTC_PhRecFineDlyByte2_SHIFT 16 -#define DDWTC_PhRecGrossDlyByte2_SHIFT 21 -#define DDWTC_PhRecFineDlyByte3_SHIFT 24 -#define DDWTC_PhRecGrossDlyByte3_SHIFT 29 - -#define DRAM_PHASE_RECOVERY_CTRL_1 0x51 -#define DPRC_PhRecFineDlyByte4_SHIFT 0 -#define DDWTC_PhRecGrossDlyByte4_SHIFT 5 -#define DDWTC_PhRecFineDlyByte5_SHIFT 8 -#define DDWTC_PhRecGrossDlyByte5_SHIFT 13 -#define DDWTC_PhRecFineDlyByte6_SHIFT 16 -#define DDWTC_PhRecGrossDlyByte6_SHIFT 21 -#define DDWTC_PhRecFineDlyByte7_SHIFT 24 -#define DDWTC_PhRecGrossDlyByte7_SHIFT 29 - -#define DRAM_ECC_PHASE_RECOVERY_CTRL 0x52 -#define DEPRC_PhRecEccDlyByte0_SHIFT 0 -#define DEPRC_PhRecEccGrossDlyByte0_SHIFT 5 - -#define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */ -#define DWLE_WrLvErr_SHIFT 0 -#define DWLE_WrLvErr_MASK 0xff - -#define DRAM_CTRL_MISC 0xa0 -#define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */ -#define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */ - -#define NB_TIME_STAMP_COUNT_LOW 0xb0 -#define TscLow_SHIFT 0 -#define TscLow_MASK 0xffffffff - -#define NB_TIME_STAMP_COUNT_HIGH 0xb4 -#define TscHigh_SHIFT 0 -#define TscHigh_Mask 0xff - -#define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/ -#define DDC_DllAdjust_SHIFT 0 -#define DDC_DllAdjust_MASK 0xff -#define DDC_DllSlower (1<<8) -#define DDC_DllFaster (1<<9) -#define DDC_WrtDqsAdjust_SHIFT 16 -#define DDC_WrtDqsAdjust_MASK 0x7 -#define DDC_WrtDqsAdjustEn (1<<19) - -#define DRAM_CTRL_SEL_LOW 0x110 -#define DCSL_DctSelHiRngEn (1<<0) -#define DCSL_DctSelHi (1<<1) -#define DCSL_DctSelIntLvEn (1<<2) -#define DCSL_MemClrInit (1<<3) /* WR only */ -#define DCSL_DctGangEn (1<<4) -#define DCSL_DctDataIntLv (1<<5) -#define DCSL_DctSelIntLvAddr_SHIFT -#define DCSL_DctSelIntLvAddr_MASK 3 -#define DCSL_DramEnable (1<<8) /* RD only */ -#define DCSL_MemClrBusy (1<<9) /* RD only */ -#define DCSL_MemCleared (1<<10) /* RD only */ -#define DCSL_DctSelBaseAddr_47_27_SHIFT 11 -#define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff - -#define DRAM_CTRL_SEL_HIGH 0x114 -#define DCSH_DctSelBaseOffset_47_26_SHIFT 10 -#define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff - -#define MEM_CTRL_CONF_LOW 0x118 -#define MCCL_MctPriCpuRd (1<<0) -#define MCCL_MctPriCpuWr (1<<1) -#define MCCL_MctPriIsocRd_SHIFT 4 -#define MCCL_MctPriIsoc_MASK 0x3 -#define MCCL_MctPriIsocWr_SHIFT 6 -#define MCCL_MctPriIsocWe_MASK 0x3 -#define MCCL_MctPriDefault_SHIFT 8 -#define MCCL_MctPriDefault_MASK 0x3 -#define MCCL_MctPriWr_SHIFT 10 -#define MCCL_MctPriWr_MASK 0x3 -#define MCCL_MctPriIsoc_SHIFT 12 -#define MCCL_MctPriIsoc_MASK 0x3 -#define MCCL_MctPriTrace_SHIFT 14 -#define MCCL_MctPriTrace_MASK 0x3 -#define MCCL_MctPriScrub_SHIFT 16 -#define MCCL_MctPriScrub_MASK 0x3 -#define MCCL_McqMedPriByPassMax_SHIFT 20 -#define MCCL_McqMedPriByPassMax_MASK 0x7 -#define MCCL_McqHiPriByPassMax_SHIFT 24 -#define MCCL_McqHiPriByPassMax_MASK 0x7 -#define MCCL_MctVarPriCntLmt_SHIFT 28 -#define MCCL_MctVarPriCntLmt_MASK 0x7 - -#define MEM_CTRL_CONF_HIGH 0x11c -#define MCCH_DctWrLimit_SHIFT 0 -#define MCCH_DctWrLimit_MASK 0x3 -#define MCCH_MctWrLimit_SHIFT 2 -#define MCCH_MctWrLimit_MASK 0x1f -#define MCCH_MctPrefReqLimit_SHIFT 7 -#define MCCH_MctPrefReqLimit_MASK 0x1f -#define MCCH_PrefCpuDis (1<<12) -#define MCCH_PrefIoDis (1<<13) -#define MCCH_PrefIoFixStrideEn (1<<14) -#define MCCH_PrefFixStrideEn (1<<15) -#define MCCH_PrefFixDist_SHIFT 16 -#define MCCH_PrefFixDist_MASK 0x3 -#define MCCH_PrefConfSat_SHIFT 18 -#define MCCH_PrefConfSat_MASK 0x3 -#define MCCH_PrefOneConf_SHIFT 20 -#define MCCH_PrefOneConf_MASK 0x3 -#define MCCH_PrefTwoConf_SHIFT 22 -#define MCCH_PrefTwoConf_MASK 0x7 -#define MCCH_PrefThreeConf_SHIFT 25 -#define MCCH_prefThreeConf_MASK 0x7 -#define MCCH_PrefDramTrainMode (1<<28) -#define MCCH_FlushWrOnStpGnt (1<<29) -#define MCCH_FlushWr (1<<30) -#define MCCH_MctScrubEn (1<<31) - - -/* Function 3 */ -#define MCA_NB_CONTROL 0x40 -#define MNCT_CorrEccEn (1<<0) -#define MNCT_UnCorrEccEn (1<<1) -#define MNCT_CrcErr0En (1<<2) /* Link 0 */ -#define MNCT_CrcErr1En (1<<3) -#define MNCT_CrcErr2En (1<<4) -#define MBCT_SyncPkt0En (1<<5) /* Link 0 */ -#define MBCT_SyncPkt1En (1<<6) -#define MBCT_SyncPkt2En (1<<7) -#define MBCT_MstrAbrtEn (1<<8) -#define MBCT_TgtAbrtEn (1<<9) -#define MBCT_GartTblEkEn (1<<10) -#define MBCT_AtomicRMWEn (1<<11) -#define MBCT_WdogTmrRptEn (1<<12) -#define MBCT_DevErrEn (1<<13) -#define MBCT_L3ArrayCorEn (1<<14) -#define MBCT_L3ArrayUncEn (1<<15) -#define MBCT_HtProtEn (1<<16) -#define MBCT_HtDataEn (1<<17) -#define MBCT_DramParEn (1<<18) -#define MBCT_RtryHt0En (1<<19) /* Link 0 */ -#define MBCT_RtryHt1En (1<<20) -#define MBCT_RtryHt2En (1<<21) -#define MBCT_RtryHt3En (1<<22) -#define MBCT_CrcErr3En (1<<23) /* Link 3*/ -#define MBCT_SyncPkt3En (1<<24) /* Link 4 */ -#define MBCT_McaUsPwDatErrEn (1<<25) -#define MBCT_NbArrayParEn (1<<26) -#define MBCT_TblWlkDatErrEn (1<<27) -#define MBCT_FbDimmCorErrEn (1<<28) -#define MBCT_FbDimmUnCorErrEn (1<<29) - - - -#define MCA_NB_CONFIG 0x44 -#define MNC_CpuRdDatErrEn (1<<1) -#define MNC_SyncOnUcEccEn (1<<2) -#define MNC_SynvPktGenDis (1<<3) -#define MNC_SyncPktPropDis (1<<4) -#define MNC_IoMstAbortDis (1<<5) -#define MNC_CpuErrDis (1<<6) -#define MNC_IoErrDis (1<<7) -#define MNC_WdogTmrDis (1<<8) -#define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */ -#define MNC_WdogTmrCntSel_2_0_MASK 0x3 -#define MNC_WdogTmrBaseSel_SHIFT 12 -#define MNC_WdogTmrBaseSel_MASK 0x3 -#define MNC_LdtLinkSel_SHIFT 14 -#define MNC_LdtLinkSel_MASK 0x3 -#define MNC_GenCrcErrByte0 (1<<16) -#define MNC_GenCrcErrByte1 (1<<17) -#define MNC_SubLinkSel_SHIFT 18 -#define MNC_SubLinkSel_MASK 0x3 -#define MNC_SyncOnWdogEn (1<<20) -#define MNC_SyncOnAnyErrEn (1<<21) -#define MNC_DramEccEn (1<<22) -#define MNC_ChipKillEccEn (1<<23) -#define MNC_IoRdDatErrEn (1<<24) -#define MNC_DisPciCfgCpuErrRsp (1<<25) -#define MNC_CorrMcaExcEn (1<<26) -#define MNC_NbMcaToMstCpuEn (1<<27) -#define MNC_DisTgtAbtCpuErrRsp (1<<28) -#define MNC_DisMstAbtCpuErrRsp (1<<29) -#define MNC_SyncOnDramAdrParErrEn (1<<30) -#define MNC_NbMcaLogEn (1<<31) - -#define MCA_NB_STATUS_LOW 0x48 -#define MNSL_ErrorCode_SHIFT 0 -#define MNSL_ErrorCode_MASK 0xffff -#define MNSL_ErrorCodeExt_SHIFT 16 -#define MNSL_ErrorCodeExt_MASK 0x1f -#define MNSL_Syndrome_15_8_SHIFT 24 -#define MNSL_Syndrome_15_8_MASK 0xff - -#define MCA_NB_STATUS_HIGH 0x4c -#define MNSH_ErrCPU_SHIFT 0 -#define MNSH_ErrCPU_MASK 0xf -#define MNSH_LDTLink_SHIFT 4 -#define MNSH_LDTLink_MASK 0xf -#define MNSH_ErrScrub (1<<8) -#define MNSH_SubLink (1<<9) -#define MNSH_McaStatusSubCache_SHIFT 10 -#define MNSH_McaStatusSubCache_MASK 0x3 -#define MNSH_Deffered (1<<12) -#define MNSH_UnCorrECC (1<<13) -#define MNSH_CorrECC (1<<14) -#define MNSH_Syndrome_7_0_SHIFT 15 -#define MNSH_Syndrome_7_0_MASK 0xff -#define MNSH_PCC (1<<25) -#define MNSH_ErrAddrVal (1<<26) -#define MNSH_ErrMiscVal (1<<27) -#define MNSH_ErrEn (1<<28) -#define MNSH_ErrUnCorr (1<<29) -#define MNSH_ErrOver (1<<30) -#define MNSH_ErrValid (1<<31) - -#define MCA_NB_ADDR_LOW 0x50 -#define MNAL_ErrAddr_31_1_SHIFT 1 -#define MNAL_ErrAddr_31_1_MASK 0x7fffffff - -#define MCA_NB_ADDR_HIGH 0x54 -#define MNAL_ErrAddr_47_32_SHIFT 0 -#define MNAL_ErrAddr_47_32_MASK 0xffff - -#define DRAM_SCRUB_RATE_CTRL 0x58 -#define SCRUB_NONE 0 -#define SCRUB_40ns 1 -#define SCRUB_80ns 2 -#define SCRUB_160ns 3 -#define SCRUB_320ns 4 -#define SCRUB_640ns 5 -#define SCRUB_1_28us 6 -#define SCRUB_2_56us 7 -#define SCRUB_5_12us 8 -#define SCRUB_10_2us 9 -#define SCRUB_20_5us 0xa -#define SCRUB_41_0us 0xb -#define SCRUB_81_9us 0xc -#define SCRUB_163_8us 0xd -#define SCRUB_327_7us 0xe -#define SCRUB_655_4us 0xf -#define SCRUB_1_31ms 0x10 -#define SCRUB_2_62ms 0x11 -#define SCRUB_5_24ms 0x12 -#define SCRUB_10_49ms 0x13 -#define SCRUB_20_97ms 0x14 -#define SCRUB_42ms 0x15 -#define SCRUB_84ms 0x16 -#define DSRC_DramScrub_SHFIT 0 -#define DSRC_DramScrub_MASK 0x1f -#define DSRC_L2Scrub_SHIFT 8 -#define DSRC_L2Scrub_MASK 0x1f -#define DSRC_DcacheScrub_SHIFT 16 -#define DSRC_DcacheScrub_MASK 0x1f -#define DSRC_L3Scrub_SHIFT 24 -#define DSRC_L3Scrub_MASK 0x1f - -#define DRAM_SCRUB_ADDR_LOW 0x5C -#define DSAL_ScrubReDirEn (1<<0) -#define DSAL_ScrubAddrLo_SHIFT 6 -#define DSAL_ScrubAddrLo_MASK 0x3ffffff - -#define DRAM_SCRUB_ADDR_HIGH 0x60 -#define DSAH_ScrubAddrHi_SHIFT 0 -#define DSAH_ScrubAddrHi_MASK 0xffff - -#define HW_THERMAL_CTRL 0x64 - -#define SW_THERMAL_CTRL 0x68 - -#define DATA_BUF_CNT 0x6c - -#define SRI_XBAR_CMD_BUF_CNT 0x70 - -#define XBAR_SRI_CMD_BUF_CNT 0x74 - -#define MCT_XBAR_CMD_BUF_CNT 0x78 - -#define ACPI_PWR_STATE_CTRL 0x80 /* till 0x84 */ - -#define NB_CONFIG_LOW 0x88 -#define NB_CONFIG_HIGH 0x8c - -#define GART_APERTURE_CTRL 0x90 - -#define GART_APERTURE_BASE 0x94 - -#define GART_TBL_BASE 0x98 - -#define GART_CACHE_CTRL 0x9c - -#define PWR_CTRL_MISC 0xa0 - -#define RPT_TEMP_CTRL 0xa4 - -#define ON_LINE_SPARE_CTRL 0xb0 - -#define SBI_P_STATE_LIMIT 0xc4 - -#define CLK_PWR_TIMING_CTRL0 0xd4 -#define CLK_PWR_TIMING_CTRL1 0xd8 -#define CLK_PWR_TIMING_CTRL2 0xdc - -#define THERMTRIP_STATUS 0xE4 - - -#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_TwoChanDRAMcap (1 << 0) -#define NBCAP_DualNodeMPcap (1 << 1) -#define NBCAP_EightNodeMPcap (1 << 2) -#define NBCAP_ECCcap (1 << 3) -#define NBCAP_ChipkillECCcap (1 << 4) -#define NBCAP_DdrMaxRate_SHIFT 5 -#define NBCAP_DdrMaxRate_MASK 7 -#define NBCAP_DdrMaxRate_400 7 -#define NBCAP_DdrMaxRate_533 6 -#define NBCAP_DdrMaxRate_667 5 -#define NBCAP_DdrMaxRate_800 4 -#define NBCAP_DdrMaxRate_1067 3 -#define NBCAP_DdrMaxRate_1333 2 -#define NBCAP_DdrMaxRate_1600 1 -#define NBCAP_DdrMaxRate_3_2G 6 -#define NBCAP_DdrMaxRate_4_0G 5 -#define NBCAP_DdrMaxRate_4_8G 4 -#define NBCAP_DdrMaxRate_6_4G 3 -#define NBCAP_DdrMaxRate_8_0G 2 -#define NBCAP_DdrMaxRate_9_6G 1 -#define NBCAP_Mem_ctrl_cap (1 << 8) -#define MBCAP_SVMCap (1<<9) -#define NBCAP_HtcCap (1<<10) -#define NBCAP_CmpCap_SHIFT 12 -#define NBCAP_CmpCap_MASK 3 -#define NBCAP_MpCap_SHIFT 16 -#define NBCAP_MpCap_MASK 7 -#define NBCAP_MpCap_1N 7 -#define NBCAP_MpCap_2N 6 -#define NBCAP_MpCap_4N 5 -#define NBCAP_MpCap_8N 4 -#define NBCAP_MpCap_32N 0 -#define NBCAP_UnGangEn_SHIFT 20 -#define NBCAP_UnGangEn_MASK 0xf -#define NBCAP_L3Cap (1<<25) -#define NBCAP_HtAcCap (1<<26) - -/* 04/04/2006 18:00 */ - -#define EXT_NB_MCA_CTRL 0x180 - -#define NB_EXT_CONF 0x188 -#define DOWNCORE_CTRL 0x190 -#define DWNCC_DisCore_SHIFT 0 -#define DWNCC_DisCore_MASK 0xf - -/* Function 5 for FBDIMM */ -#define FBD_DRAM_TIMING_LOW - -#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) -#define ConnectionPending (1 << 4) - -// Use the LAPIC timer count register to hold each core's init status -// Format: byte 0 - state -// byte 1 - fid_max -// byte 2 - nb_cof_vid_update -// byte 3 - apic id - -#define LAPIC_MSG_REG 0x380 -#define F10_APSTATE_STARTED 0x13 // start of AP execution -#define F10_APSTATE_ASLEEP 0x14 // AP sleeping -#define F10_APSTATE_STOPPED 0x15 // allow AP to stop -#define F10_APSTATE_RESET 0x01 // waiting for warm reset - -#define MAX_CORES_SUPPORTED 128 - -#include "nums.h" - -#if NODE_NUMS == 64 - #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else - #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -/* Include wrapper for MCT (works for DDR2 or DDR3) */ -#include <northbridge/amd/amdmct/wrappers/mcti.h> - -struct link_pair_t { - pci_devfn_t udev; - u32 upos; - u32 uoffs; - pci_devfn_t dev; - u32 pos; - u32 offs; - u8 host; - u8 nodeid; - u8 linkn; - u8 rsv; -} __packed; - -struct nodes_info_t { - u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8 - u32 groups_in_plane; // could be 1, 2, 3, 4, 5 - u32 planes; // could be 1, 2 - u32 up_planes; // down planes will be [up_planes, planes) -} __packed; - -struct ht_link_config { - uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default) -}; - -/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ - -struct sys_info { - int32_t needs_reset; - - u8 ln[NODE_NUMS*NODE_NUMS];// [0, 3] link n, [4, 7] will be hop num - u16 ln_tn[NODE_NUMS*8]; // for 0x0zzz: bit [0,7] target node num, bit[8,11] respone link from target num; 0x80ff mean not inited, 0x4yyy mean non coherent and yyy is link pair index - struct nodes_info_t nodes_info; - u32 nodes; - - u8 host_link_freq[NODE_NUMS*8]; // record freq for every link from cpu, 0x0f means don't need to touch it - u16 host_link_freq_cap[NODE_NUMS*8]; //cap - - struct ht_link_config ht_link_cfg; - - u32 segbit; - u32 sbdn; - u32 sblk; - u32 sbbusn; - - u32 ht_c_num; - u32 ht_c_conf_bus[HC_NUMS]; // 4-->32 - - struct link_pair_t link_pair[HC_NUMS*4];// enough? only in_conherent, 32 chain and every chain have 4 HT device - u32 link_pair_num; - - struct mem_controller ctrl[NODE_NUMS]; - - struct MCTStatStruc MCTstat; - struct DCTStatStruc DCTstatA[NODE_NUMS]; -} __packed; - -struct device *get_node_pci(u32 nodeid, u32 fn); - -void showallroutes(int level, pci_devfn_t dev); - -void setup_resource_map_offset(const u32 *register_values, u32 max, u32 - offset_pci_dev, u32 offset_io_base); - -void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 - offset_pci_dev, u32 offset_io_base); - -void setup_resource_map_x(const u32 *register_values, u32 max); -void setup_resource_map(const u32 *register_values, u32 max); -void setup_mb_resource_map(void); - -/* reset_test.c */ -u32 cpu_init_detected(u8 nodeid); -u32 bios_reset_detected(void); -u32 cold_reset_detected(void); -u32 other_reset_detected(void); -u32 warm_reset_detect(u8 nodeid); -void distinguish_cpu_resets(u8 nodeid); -u32 get_sblk(void); -u8 get_sbbusn(u8 sblk); -void set_bios_reset(void); - -#include "northbridge/amd/amdht/porting.h" -BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); - -struct acpi_rsdp; - -unsigned long northbridge_write_acpi_tables(struct device *device, - unsigned long start, - struct acpi_rsdp *rsdp); -void northbridge_acpi_write_vars(struct device *device); - -#endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl deleted file mode 100644 index 6e2118d1ae..0000000000 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ /dev/null @@ -1,321 +0,0 @@ -// -// This file is part of the coreboot project. -// -// Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering -// Copyright (C) 2007 Advanced Micro Devices, Inc. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; version 2 of the License. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// - -//AMD FAM10 util for BUSB and res range - -Scope (\_SB) -{ - - Name (OSTB, Ones) - Method (OSVR, 0, NotSerialized) - { - If (LEqual (^OSTB, Ones)) - { - Store (0x00, ^OSTB) - } - - Return (^OSTB) - } - - Method (SEQL, 2, Serialized) - { - Store (SizeOf (Arg0), Local0) - Store (SizeOf (Arg1), Local1) - If (LNot (LEqual (Local0, Local1))) { Return (Zero) } - - Name (BUF0, Buffer (Local0) {}) - Store (Arg0, BUF0) - Name (BUF1, Buffer (Local0) {}) - Store (Arg1, BUF1) - Store (Zero, Local2) - While (LLess (Local2, Local0)) - { - Store (DerefOf (Index (BUF0, Local2)), Local3) - Store (DerefOf (Index (BUF1, Local2)), Local4) - If (LNot (LEqual (Local3, Local4))) { Return (Zero) } - - Increment (Local2) - } - - Return (One) - } - - - Method (DADD, 2, NotSerialized) - { - Store(Arg1, Local0) - Store(Arg0, Local1) - Add(ShiftLeft(Local1,16), Local0, Local0) - Return (Local0) - } - - - Method (GHCE, 1, NotSerialized) // check if the HC enabled - { - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) } - Else { Return (0x00) } - } - - Method (GHCN, 1, NotSerialized) // get the node num for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight(And (Local1, 0xfc), 0x02), Local0) - Return (Local0) - } - - Method (GHCL, 1, NotSerialized) // get the link num on node for the HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - Store (ShiftRight(And (Local1, 0x700), 0x08), Local0) - Return (Local0) - } - - Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC - { - Store (0x00, Local0) - Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) - Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 - Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 - Store (And (ShiftRight(Local1, Local2), 0xff), Local0) - Return (Local0) - } - - Method (GBUS, 2, NotSerialized) - { - Store (0x00, Local0) - While (LLess (Local0, 0x20)) // 32 ht links - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) - { - Return (ShiftRight (And (Local1, 0x000FF000), 0x0c)) - } - } - } - - Increment (Local0) - } - - Return (0x00) - } - - Method (GWBN, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0000, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0001,,,) - }) - CreateWordField (BUF0, 0x08, BMIN) - CreateWordField (BUF0, 0x0A, BMAX) - CreateWordField (BUF0, 0x0E, BLEN) - Store (0x00, Local0) - While (LLess (Local0, 0x20)) - { - Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, ShiftRight (And (Local1, 0xfc), 0x02))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0700), 0x08)))) - { - Store (ShiftRight (And (Local1, 0x000FF000), 0x0c), BMIN) - Store (ShiftRight (Local1, 0x14), BMAX) - Subtract (BMAX, BMIN, BLEN) - Increment (BLEN) - Return (RTAG (BUF0)) - } - } - } - - Increment (Local0) - } - - Return (RTAG (BUF0)) - } - - Method (GMEM, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000001,,, - , AddressRangeMemory, TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, MMIN) - CreateDWordField (BUF0, 0x0E, MMAX) - CreateDWordField (BUF0, 0x16, MLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem) *2 (base, limit) - { - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x3f))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) - { - Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) - Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) - Or (MMAX, 0xFFFF, MMAX) - Subtract (MMAX, MMIN, MLEN) - Increment (MLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (BUF0, Local3) - } - - Return (Local3) - } - - Method (GIOR, 2, Serialized) - { - Name (BUF0, ResourceTemplate () - { - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0x00000000, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00000001,,, - , TypeStatic) - }) - CreateDWordField (BUF0, 0x0A, PMIN) - CreateDWordField (BUF0, 0x0E, PMAX) - CreateDWordField (BUF0, 0x16, PLEN) - Store (0x00, Local0) - Store (0x00, Local4) - Store (0x00, Local3) - While (LLess (Local0, 0x40)) // 0x20 ht links * 2 (base, limit) - { - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) - Increment (Local0) - Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) - If (LEqual (And (Local1, 0x03), 0x03)) - { - If (LEqual (Arg0, And (Local2, 0x3f))) - { - If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x70), 0x04)))) - { - Store (And (Local1, 0x01FFF000), PMIN) - Store (And (Local2, 0x01FFF000), PMAX) - Or (PMAX, 0x0FFF, PMAX) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - If (LGreater (PMAX, PMIN)) - { - If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) - { - Store (0x0D00, PMIN) - Subtract (PMAX, PMIN, PLEN) - Increment (PLEN) - } - - Store (RTAG (BUF0), Local3) - Increment (Local4) - } - - If (And (Local1, 0x10)) - { - Store (0x03B0, PMIN) - Store (0x03DF, PMAX) - Store (0x30, PLEN) - - If (Local4) - { - Concatenate (RTAG (BUF0), Local3, Local5) - Store (Local5, Local3) - } - Else - { - Store (RTAG (BUF0), Local3) - } - } - } - - Increment (Local4) - } - } - } - - Increment (Local0) - } - - If (LNot (Local4)) - { - Store (RTAG (BUF0), Local3) - } - - Return (Local3) - } - - Method (RTAG, 1, NotSerialized) - { - Store (Arg0, Local0) - Store (SizeOf (Local0), Local1) - Subtract (Local1, 0x02, Local1) - Multiply (Local1, 0x08, Local1) - CreateField (Local0, 0x00, Local1, RETB) - Store (RETB, Local2) - Return (Local2) - } -} diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c deleted file mode 100644 index 23e92323a8..0000000000 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <console/console.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include "raminit.h" -#include <northbridge/amd/amdmct/amddefs.h> - -#if !ENV_PCI_SIMPLE_DEVICE -u32 Get_NB32(u32 dev, u32 reg) -{ - return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); -} -#endif - -uint64_t mctGetLogicalCPUID(u32 Node) -{ - /* Converts the CPUID to a logical ID MASK that is used to check - CPU version support versions */ - u32 dev; - u32 val, valx; - u32 family, model, stepping; - uint64_t ret; - - if (Node == 0xFF) { /* current node */ - val = cpuid_eax(0x80000001); - } else { - dev = PA_NBMISC(Node); - val = Get_NB32(dev, 0xfc); - } - - family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff); - model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0); - stepping = val & 0x0f; - - valx = (family << 12) | (model << 4) | (stepping); - - switch (valx) { - case 0x10000: - ret = AMD_DR_A0A; - break; - case 0x10001: - ret = AMD_DR_A1B; - break; - case 0x10002: - ret = AMD_DR_A2; - break; - case 0x10020: - ret = AMD_DR_B0; - break; - case 0x10021: - ret = AMD_DR_B1; - break; - case 0x10022: - ret = AMD_DR_B2; - break; - case 0x10023: - ret = AMD_DR_B3; - break; - case 0x10042: - ret = AMD_RB_C2; - break; - case 0x10043: - ret = AMD_RB_C3; - break; - case 0x10062: - ret = AMD_DA_C2; - break; - case 0x10063: - ret = AMD_DA_C3; - break; - case 0x10080: - ret = AMD_HY_D0; - break; - case 0x10081: - case 0x10091: - ret = AMD_HY_D1; - break; - case 0x100a0: - ret = AMD_PH_E0; - break; - case 0x15012: - case 0x1501f: - ret = AMD_OR_B2; - break; - case 0x15020: - case 0x15101: - ret = AMD_OR_C0; - break; - default: - /* FIXME: mabe we should die() here. */ - printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! %08x\n", valx); - ret = 0; - } - - return ret; -} diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c deleted file mode 100644 index f2d5f89ec7..0000000000 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "northbridge/amd/amdfam10/early_ht.c" - -static void bootblock_northbridge_init(void) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); -} diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h deleted file mode 100644 index daf429d91a..0000000000 --- a/src/northbridge/amd/amdfam10/chip.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AMD_FAM10_CHIP_H_ -#define _AMD_FAM10_CHIP_H_ - -#include <stdint.h> - -struct northbridge_amd_amdfam10_config { - uint64_t maximum_memory_capacity; -}; - -#endif /* _AMD_FAM10_CHIP_H_ */ diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c deleted file mode 100644 index 5090352e9a..0000000000 --- a/src/northbridge/amd/amdfam10/debug.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "debug.h" -#include <console/console.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <delay.h> - -void print_debug_addr(const char *str, void *val) -{ -#if CONFIG(DEBUG_CAR) - printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); -#endif -} - -void print_debug_pci_dev(u32 dev) -{ - printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); -} - -void print_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16)); - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -void print_pci_devices_on_bus(u32 busn) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16)); - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) -{ - int i; - print_debug_pci_dev(dev); - int j; - int end = start_reg + size; - - for (i = start_reg; i < end; i+=4) { - u32 val; - if ((i & 0x0f) == 0) { - printk(BIOS_DEBUG, "\n%04x:",i); - } - val = pci_read_config32(dev, i); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, " %02x", val & 0xff); - val >>= 8; - } - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_device(u32 dev) -{ - dump_pci_device_range(dev, 0, 4096); -} - -void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, - u32 size) -{ - int i; - int end = start + size; - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg); - - for (i = start; i < end; i++) { - u32 val; - int j; - printk(BIOS_DEBUG, "\n%02x:",i); - val = pci_read_config32_index_wait(dev, index_reg, i); - for (j = 0; j < 4; j++) { - printk(BIOS_DEBUG, " %02x", val & 0xff); - val >>= 8; - } - - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_device_index_wait(u32 dev, u32 index_reg) -{ - dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); - dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz -} - -void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) -{ - int i; - print_debug_pci_dev(dev); - - printk(BIOS_DEBUG, " index reg: %04x type: %02x", index_reg, type); - - type<<=28; - - for (i = 0; i < length; i++) { - u32 val; - if ((i & 0x0f) == 0) { - printk(BIOS_DEBUG, "\n%02x:",i); - } - val = pci_read_config32_index(dev, index_reg, i|type); - printk(BIOS_DEBUG, " %08x", val); - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -void dump_pci_devices_on_bus(u32 busn) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - u32 id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - - if (((dev>>12) & 0x07) == 0) { - u8 hdr_type; - hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if ((hdr_type & 0x80) != 0x80) { - dev += PCI_DEV(0,0,7); - } - } - } -} - -#if CONFIG(DEBUG_SMBUS) -void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 0; i < DIMM_SOCKETS; i++) { - u32 device; - device = ctrl->spd_addr[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - u8 byte; - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - device = ctrl->spd_addr[i+DIMM_SOCKETS]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - u8 byte; - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - } -} - -void dump_smbus_registers(void) -{ - u32 device; - printk(BIOS_DEBUG, "\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (smbus_read_byte(device, 0) < 0) continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - u8 byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ",j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } -} -#endif - -void dump_io_resources(u32 port) -{ - - int i; - udelay(2000); - printk(BIOS_DEBUG, "%04x:\n", port); - for (i = 0; i < 256; i++) { - u8 val; - if ((i & 0x0f) == 0) { - printk(BIOS_DEBUG, "%02x:", i); - } - val = inb(port); - printk(BIOS_DEBUG, " %02x",val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } - port++; - } -} - -#if CONFIG(DIMM_DDR2) -void print_tx(const char *strval, u32 val) -{ -#if CONFIG(DEBUG_RAM_SETUP) - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -#endif -} - -void print_t(const char *strval) -{ -#if CONFIG(DEBUG_RAM_SETUP) - printk(BIOS_DEBUG, "%s", strval); -#endif -} -#endif /* CONFIG_DIMM_DDR2 */ - -void print_tf(const char *func, const char *strval) -{ -#if CONFIG(DEBUG_RAM_SETUP) - printk(BIOS_DEBUG, "%s: %s", func, strval); -#endif -} diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h deleted file mode 100644 index 01d87d96af..0000000000 --- a/src/northbridge/amd/amdfam10/debug.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_DEBUG_H -#define AMDFAM10_DEBUG_H - -#include <stdint.h> -#include "pci.h" - -void print_debug_addr(const char *str, void *val); -void print_debug_pci_dev(u32 dev); -void print_pci_devices(void); -void print_pci_devices_on_bus(u32 busn); -void dump_pci_device_range(u32 dev, u32 start_reg, u32 size); -void dump_pci_device(u32 dev); -void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, - u32 size); -void dump_pci_device_index_wait(u32 dev, u32 index_reg); -void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length); -void dump_pci_devices(void); -void dump_pci_devices_on_bus(u32 busn); - -#if CONFIG(DEBUG_SMBUS) -void dump_spd_registers(const struct mem_controller *ctrl); -void dump_smbus_registers(void); -#endif - -void dump_io_resources(u32 port); - -void print_tx(const char *strval, u32 val); -void print_t(const char *strval); -void print_tf(const char *func, const char *strval); -#endif diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c deleted file mode 100644 index dc0f6840e2..0000000000 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "early_ht.h" -#include <stdint.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> - -// For SB HT chain only -// mmconf is not ready yet -void set_bsp_node_CHtExtNodeCfgEn(void) -{ -#if CONFIG(EXT_RT_TBL_SUPPORT) - u32 dword; - dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); - dword |= (1<<27) | (1<<25); - /* CHtExtNodeCfgEn: coherent link extended node configuration enable, - Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0] - ---- 32 nodes now only - It can be used even nodes less than 8 nodes. - We can have 8 more device on bus 0 in that case - */ - - /* CHtExtAddrEn */ - pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword); - // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. -#endif -} - -void enumerate_ht_chain(void) -{ -#if CONFIG_HT_CHAIN_UNITID_BASE != 0 -/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), - if so, don't need to go through the chain */ - - /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a CPU has multiple - * non Coherent links the appropriate bus registers for the - * links needs to be programed to point at bus 0. - */ - unsigned int next_unitid, last_unitid = 0; -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - // let't record the device of last ht device, So we can set the - // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned int real_last_unitid = 0; - u8 real_last_pos = 0; - int ht_dev_num = 0; // except host_bridge - u8 end_used = 0; -#endif - - next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; - do { - u32 id; - u8 hdr_type, pos; - last_unitid = next_unitid; - - id = pci_io_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); - /* If the chain is enumerated quit */ - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) - { - break; - } - - hdr_type = pci_io_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE); - pos = 0; - hdr_type &= 0x7f; - - if ((hdr_type == PCI_HEADER_TYPE_NORMAL) || - (hdr_type == PCI_HEADER_TYPE_BRIDGE)) - { - pos = pci_io_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST); - } - while (pos != 0) { - u8 cap; - cap = pci_io_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); - if (cap == PCI_CAP_ID_HT) { - u16 flags; - /* Read and write and reread flags so the link - * direction bit is valid. - */ - flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); - flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); - if ((flags >> 13) == 0) { - unsigned int count; - unsigned int ctrl, ctrl_off; - pci_devfn_t devx; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (next_unitid >= 0x18) { - if (!end_used) { - next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; - } else { - goto out; - } - } - real_last_unitid = next_unitid; - real_last_pos = pos; - ht_dev_num++; -#endif - #if !CONFIG_HT_CHAIN_END_UNITID_BASE - if (!next_unitid) - goto out; - #endif - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - devx = PCI_DEV(0, next_unitid, 0); - next_unitid += count; - - pci_io_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); - - /* Test for end of chain */ - ctrl_off = ((flags >> 10) & 1)? - PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; - - do { - ctrl = pci_io_read_config16(devx, pos + ctrl_off); - /* Is this the end of the hypertransport chain? */ - if (ctrl & (1 << 6)) { - goto out; - } - - if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have - * a CRC error. - * Sometimes this can happen due to link - * retrain, so lets knock it down and see - * if its transient - */ - ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc - pci_io_write_config16(devx, pos + ctrl_off, ctrl); - ctrl = pci_io_read_config16(devx, pos + ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - // can not clear the error - break; - } - } - } while ((ctrl & (1 << 5)) == 0); - - break; - } - } - pos = pci_io_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT); - } - } while (last_unitid != next_unitid); - -out: ; -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { - u16 flags; - flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); - } -#endif - -#endif -} diff --git a/src/northbridge/amd/amdfam10/early_ht.h b/src/northbridge/amd/amdfam10/early_ht.h deleted file mode 100644 index 67476fd849..0000000000 --- a/src/northbridge/amd/amdfam10/early_ht.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef EARLY_HT_H -#define EARLY_HT_H - -void set_bsp_node_CHtExtNodeCfgEn(void); -void enumerate_ht_chain(void); - -#endif diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c deleted file mode 100644 index 94ec831d65..0000000000 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootstate.h> -#include <device/pci.h> -#include <stdint.h> - -#include <cpu/amd/amdfam10_sysconf.h> - - -/* Need pci1234 array - * pci1234[0] will record sblink and bus range - * pci1234[i] will record ht chain i. - * It will keep the sequence when some ht io card is not installed. - * - * 1n: 8 - * 2n: 7x2 - * 3n: 6x3 - * 4n: 5x4 - * 5n: 4x5 - * 6n: 3x6 - * 7n: 2x7 - * 8n: 1x8 - * - * 8n(4x2): 8x4 - * 16n(4x4): 16*2 - * 20n(4x5): 20x1 - * 32n(4x4+4x4): 16x1 - * - * Total: xxx: I just want to use 32 instead, If you have more, you may need to - * reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk) - * - * Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c - * on MB dir. How about co-processor on socket 1 on 2 way system. - * or socket 2, and socket3 on 4 way system? treat that as one hc too! - * - */ - -#include "northbridge.h" - -void get_pci1234(void) -{ - - int i,j; - u32 dword; - - dword = sysconf.sblk<<8; - dword |= 1; - sysconf.pci1234[0] = dword; // sblink - sysconf.hcid[0] = 0; - - /* about hardcode numbering for HT_IO support - set the node_id and link_id that could have ht chain in the one array, - then check if is enabled.... then update final value - */ - - //here we need to set hcdn - //1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set - //2. so at the same time we need update hsdn with hcdn_reg here - - for (j = 0; j < sysconf.ht_c_num; j++) { - u32 dwordx; - dwordx = sysconf.ht_c_conf_bus[j]; - dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits - if ((dwordx & 0x7fd) == dword) { //SBLINK - sysconf.pci1234[0] = dwordx; - sysconf.hcdn[0] = sysconf.hcdn_reg[j]; - continue; - } - if ((dwordx & 1)) { - // We need to find out the number of HC - // for exact match - for (i = 1; i < sysconf.hc_possible_num; i++) { - if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn - sysconf.pci1234[i] = dwordx; - sysconf.hcdn[i] = sysconf.hcdn_reg[j]; - break; - } - } - // for 0xffc match or same node - for (i = 1; i < sysconf.hc_possible_num; i++) { - if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) { - sysconf.pci1234[i] = dwordx; - sysconf.hcdn[i] = sysconf.hcdn_reg[j]; - break; - } - } - } - } - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 1)) { - sysconf.pci1234[i] = 0; - sysconf.hcdn[i] = 0x20202020; - } - sysconf.hcid[i] = 0; - } -} - -void get_default_pci1234(int mb_hc_possible) -{ - int i; - - for (i = 0; i < mb_hc_possible; i++) { - sysconf.pci1234[i] = 0x0000ffc; - sysconf.hcdn[i] = 0x20202020; - } - sysconf.hc_possible_num = mb_hc_possible; - get_pci1234(); -} - -static void amd_bs_sysconf(void *arg) -{ - /* Prepare sysconf structures, which are used to generate IRQ, - * MP and ACPI table entries. - */ - get_bus_conf(); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, amd_bs_sysconf, NULL); diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c deleted file mode 100644 index 8499dbb623..0000000000 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_ops.h> - -#include <cpu/amd/amdfam10_sysconf.h> -#include "northbridge.h" -#include "amdfam10.h" -#include "ht_config.h" - -struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct dram_base_mask_t d; - struct device *dev = __f1_dev[0]; - - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; - - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; - return d; -} - -void set_config_map_reg(struct bus *link) -{ - u32 tempreg; - u32 i; - u32 ht_c_index = get_ht_c_index(link); - u32 linkn = link->link_num & 0x0f; - u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; - u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; - u32 nodeid = amdfam10_nodeid(link->dev); - - tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; - tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - - for (i = 0; i < sysconf.nodes; i++) { - struct device *dev = __f1_dev[i]; - pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); - } -} - -void clear_config_map_reg(struct bus *link) -{ - u32 i; - u32 ht_c_index = get_ht_c_index(link); - - for (i = 0; i < sysconf.nodes; i++) { - struct device *dev = __f1_dev[i]; - pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); - } -} - - -static u32 ht_c_key(struct bus *link) -{ - u32 nodeid = amdfam10_nodeid(link->dev); - u32 linkn = link->link_num & 0x0f; - u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; - return val; -} - -static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) -{ - u32 ht_c_index = 0; - - for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { - return ht_c_index; - } - } - - for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { - if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { - return ht_c_index; - } - } - - return -1; -} - -u32 get_ht_c_index(struct bus *link) -{ - u32 val = ht_c_key(link); - return get_ht_c_index_by_key(val, &sysconf); -} - -void store_ht_c_conf_bus(struct bus *link) -{ - u32 val = ht_c_key(link); - u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); - - u32 segn = (link->subordinate >> 8) & 0x0f; - u32 busn_min = link->secondary & 0xff; - u32 busn_max = link->subordinate & 0xff; - - val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); - - sysconf.ht_c_conf_bus[ht_c_index] = val; - sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; - sysconf.ht_c_num++; -} - -u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index = 0; index < 256; index++) { - - if (index + 4 >= ARRAY_SIZE(sysconf.conf_io_addrx)) - die("Error! Out of bounds read in %s:%s\n", __FILE__, __func__); - - if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f); - sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - -u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index = 0; index < 64; index++) { - - if (index + 8 >= ARRAY_SIZE(sysconf.conf_mmio_addrx)) - die("Error! Out of bounds read in %s:%s\n", __FILE__, __func__); - - if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f); - sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - - -void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 io_min, u32 io_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0xc0)>>3; - - val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit - - if (sysconf.io_addr_num < (index+1)) - sysconf.io_addr_num = index+1; -} - - -void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0x80)>>3; - - val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit - - if (sysconf.mmio_addr_num<(index+1)) - sysconf.mmio_addr_num = index+1; -} - - -void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h deleted file mode 100644 index 748a9818c1..0000000000 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AMDFAM10_HT_CONFIG_H__ -#define __AMDFAM10_HT_CONFIG_H__ - -typedef struct amdfam10_sysconf_t sys_info_conf_t; - -/* FIXME */ -u32 amdfam10_nodeid(struct device *dev); -extern struct device *__f1_dev[]; - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -struct dram_base_mask_t get_dram_base_mask(u32 nodeid); - -u32 get_ht_c_index(struct bus *link); -void store_ht_c_conf_bus(struct bus *link); - -void set_config_map_reg(struct bus *link); -void clear_config_map_reg(struct bus *link); - - -void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 io_min, u32 io_max); - -void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max); - - -u32 get_io_addr_index(u32 nodeid, u32 linkn); -u32 get_mmio_addr_index(u32 nodeid, u32 linkn); - -void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max); - -void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes); - -#endif diff --git a/src/northbridge/amd/amdfam10/inline_helper.c b/src/northbridge/amd/amdfam10/inline_helper.c deleted file mode 100644 index 7f260318f7..0000000000 --- a/src/northbridge/amd/amdfam10/inline_helper.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> - -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c deleted file mode 100644 index 384772374b..0000000000 --- a/src/northbridge/amd/amdfam10/link_control.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Configure various power control registers, including processor - * boost support. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <cpu/amd/model_10xxx_rev.h> -#include <types.h> - -#include "amdfam10.h" - -static void nb_control_init(struct device *dev) -{ - uint8_t enable_c_states; - uint8_t enable_cc6; - uint32_t dword; - - printk(BIOS_DEBUG, "NB: Function 4 Link Control.. "); - - /* Configure L3 Power Control */ - dword = pci_read_config32(dev, 0x1c4); - dword |= (0x1 << 8); /* L3PwrSavEn = 1 */ - pci_write_config32(dev, 0x1c4, dword); - - if (is_fam15h()) { - /* Configure L3 Control 2 */ - dword = pci_read_config32(dev, 0x1cc); - dword &= ~(0x7 << 6); /* ImplRdProjDelayThresh = 0x2 */ - dword |= (0x2 << 6); - pci_write_config32(dev, 0x1cc, dword); - - /* Configure TDP Accumulator Divisor Control */ - dword = pci_read_config32(dev, 0x104); - dword &= ~(0xfff << 2); /* TdpAccDivRate = 0xc8 */ - dword |= (0xc8 << 2); - dword &= ~0x3; /* TdpAccDivVal = 0x1 */ - dword |= 0x1; - pci_write_config32(dev, 0x104, dword); - - /* Configure Sample and Residency Timers */ - dword = pci_read_config32(dev, 0x110); - dword &= ~0xfff; /* CSampleTimer = 0x1 */ - dword |= 0x1; - pci_write_config32(dev, 0x110, dword); - - /* Configure APM TDP Control */ - dword = pci_read_config32(dev, 0x16c); - dword |= (0x1 << 4); /* ApmTdpLimitIntEn = 1 */ - pci_write_config32(dev, 0x16c, dword); - - /* Enable APM */ - dword = pci_read_config32(dev, 0x15c); - dword |= (0x1 << 7); /* ApmMasterEn = 1 */ - pci_write_config32(dev, 0x15c, dword); - - enable_c_states = 0; - enable_cc6 = 0; -#if CONFIG(HAVE_ACPI_TABLES) - uint8_t nvram; - - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - enable_cc6 = !!nvram; -#endif - - if (enable_c_states) { - /* Configure C-state Control 1 */ - dword = pci_read_config32(dev, 0x118); - dword |= (0x1 << 24); /* PwrGateEnCstAct1 = 1 */ - dword &= ~(0x7 << 21); /* ClkDivisorCstAct1 = 0x0 */ - dword &= ~(0x3 << 18); /* CacheFlushTmrSelCstAct1 = 0x1 */ - dword |= (0x1 << 18); - dword |= (0x1 << 17); /* CacheFlushEnCstAct1 = 1 */ - dword |= (0x1 << 16); /* CpuPrbEnCstAct1 = 1 */ - dword &= ~(0x1 << 8); /* PwrGateEnCstAct0 = 0 */ - dword &= ~(0x7 << 5); /* ClkDivisorCstAct0 = 0x0 */ - dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x2 */ - dword |= (0x2 << 2); - dword |= (0x1 << 1); /* CacheFlushEnCstAct0 = 1 */ - dword |= 0x1; /* CpuPrbEnCstAct0 = 1 */ - pci_write_config32(dev, 0x118, dword); - - /* Configure C-state Control 2 */ - dword = pci_read_config32(dev, 0x11c); - dword &= ~(0x1 << 8); /* PwrGateEnCstAct2 = 0 */ - dword &= ~(0x7 << 5); /* ClkDivisorCstAct2 = 0x0 */ - dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x0 */ - dword &= ~(0x1 << 1); /* CacheFlushEnCstAct0 = 0 */ - dword &= ~(0x1); /* CpuPrbEnCstAct0 = 0 */ - pci_write_config32(dev, 0x11c, dword); - - /* Configure C-state Policy Control 1 */ - dword = pci_read_config32(dev, 0x128); - dword &= ~(0x7f << 5); /* CacheFlushTmr = 0x28 */ - dword |= (0x28 << 5); - dword &= ~0x1; /* CoreCstateMode = !enable_cc6 */ - dword |= ((enable_cc6)?0:1); - pci_write_config32(dev, 0x128, dword); - } - } - - printk(BIOS_DEBUG, "done.\n"); -} - - -static struct device_operations mcf4_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nb_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf4_driver_fam10 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1204, -}; - -static const struct pci_driver mcf4_driver_fam15_model10 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1404, -}; - -static const struct pci_driver mcf4_driver_fam15 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1604, -}; diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c deleted file mode 100644 index b0a1ab679a..0000000000 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 by Eric Biederman - * Copyright (C) Stefan Reinauer - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Turn off machine check triggers when reading - * pci space where there are no devices. - * This is necessary when scanning the bus for - * devices which is done by the kernel - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <lib.h> -#include <cbmem.h> -#include <cpu/amd/model_10xxx_rev.h> -#include <types.h> - -#include "amdfam10.h" - -/** - * @brief Read resources for AGP aperture - * - * @param dev - * - * There is only one AGP aperture resource needed. The resource is added to - * the northbridge of BSP. - * - * The same trick can be used to augment legacy VGA resources which can - * be detect by generic pci reousrce allocator for VGA devices. - * BAD: it is more tricky than I think, the resource allocation code is - * implemented in a way to NOT DOING legacy VGA resource allocation on - * purpose :-(. - */ -static void mcf3_read_resources(struct device *dev) -{ - struct resource *resource; - unsigned char gart; - /* Read the generic PCI resources */ - pci_dev_read_resources(dev); - - /* If we are not the first processor don't allocate the gart apeture */ - if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) { - return; - } - - gart = 1; - get_option(&gart, "gart"); - - if (gart) { - /* Add a Gart apeture resource */ - resource = new_resource(dev, 0x94); - resource->size = CONFIG_AGP_APERTURE_SIZE; - resource->align = log2(resource->size); - resource->gran = log2(resource->size); - resource->limit = 0xffffffff; /* 4G */ - resource->flags = IORESOURCE_MEM; - } -} - -static void set_agp_aperture(struct device *dev, uint32_t pci_id) -{ - uint32_t dword; - struct resource *resource; - - resource = probe_resource(dev, 0x94); - if (resource) { - struct device *pdev; - u32 gart_base, gart_acr; - - /* Remember this resource has been stored */ - resource->flags |= IORESOURCE_STORED; - - /* Find the size of the GART aperture */ - gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0); - - /* Get the base address */ - gart_base = ((resource->base) >> 25) & 0x00007fff; - - /* Update the other northbriges */ - pdev = 0; - while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, pci_id, pdev))) { - /* Store the GART size but don't enable it */ - pci_write_config32(pdev, 0x90, gart_acr); - - /* Store the GART base address */ - pci_write_config32(pdev, 0x94, gart_base); - - /* Don't set the GART Table base address */ - pci_write_config32(pdev, 0x98, 0); - - /* Report the resource has been stored... */ - report_resource_stored(pdev, resource, " <gart>"); - - /* Errata 540 workaround */ - dword = pci_read_config32(pdev, 0x90); - dword |= 0x1 << 6; /* DisGartTblWlkPrb = 0x1 */ - pci_write_config32(pdev, 0x90, dword); - } - } -} - -static void mcf3_set_resources_fam10h(struct device *dev) -{ - /* Set the gart aperture */ - set_agp_aperture(dev, 0x1203); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); -} - -static void mcf3_set_resources_fam15h_model10(struct device *dev) -{ - /* Set the gart aperture */ - set_agp_aperture(dev, 0x1403); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); -} - -static void mcf3_set_resources_fam15h(struct device *dev) -{ - /* Set the gart aperture */ - set_agp_aperture(dev, 0x1603); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); -} - -static void misc_control_init(struct device *dev) -{ - uint32_t dword; - uint8_t nvram; - uint8_t boost_limit; - uint8_t current_boost; - - printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); - -#if CONFIG(DIMM_DDR3) && !CONFIG(NORTHBRIDGE_AMD_AGESA) - uint8_t node; - uint8_t slot; - uint8_t dimm_present; - - /* Restore DRAM MCA registers */ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info) { - node = PCI_SLOT(dev->path.pci.devfn) - 0x18; - - /* Check node for installed DIMMs */ - dimm_present = 0; - - /* Check all slots for installed DIMMs */ - for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { - if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { - dimm_present = 1; - break; - } - } - - if (dimm_present) { - uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); - uint32_t mc4_status_low = pci_read_config32(dev, 0x48); - if ((mc4_status_high & (0x1 << 31)) && (mc4_status_high != 0xffffffff)) { - printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" - "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); - } - - /* Clear MC4 error status */ - pci_write_config32(dev, 0x48, 0x0); - pci_write_config32(dev, 0x4c, 0x0); - } - } -#endif - - /* Disable Machine checks from Invalid Locations. - * This is needed for PC backwards compatibility. - */ - dword = pci_read_config32(dev, 0x44); - dword |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, dword); - - boost_limit = 0xf; - if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS) - boost_limit = nvram & 0xf; - - /* Set P-state maximum value */ - dword = pci_read_config32(dev, 0xdc); - current_boost = (dword >> 8) & 0x7; - if (boost_limit > current_boost) - boost_limit = current_boost; - dword &= ~(0x7 << 8); - dword |= (boost_limit & 0x7) << 8; - pci_write_config32(dev, 0xdc, dword); - - printk(BIOS_DEBUG, "done.\n"); -} - - -static struct device_operations mcf3_ops_fam10h = { - .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources_fam10h, - .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static struct device_operations mcf3_ops_fam15h_model10 = { - .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources_fam15h_model10, - .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static struct device_operations mcf3_ops_fam15h = { - .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources_fam15h, - .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf3_driver __pci_driver = { - .ops = &mcf3_ops_fam10h, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1203, -}; - -static const struct pci_driver mcf3_driver_fam15_model10 __pci_driver = { - .ops = &mcf3_ops_fam15h_model10, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1403, -}; - -static const struct pci_driver mcf3_driver_fam15 __pci_driver = { - .ops = &mcf3_ops_fam15h, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1603, -}; diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c deleted file mode 100644 index a9bdb18415..0000000000 --- a/src/northbridge/amd/amdfam10/nb_control.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Configure various power control registers, including processor boost - * and TDP monitoring support. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/amd/model_10xxx_rev.h> - -#include "amdfam10.h" - -static void nb_control_init(struct device *dev) -{ - uint32_t dword; - uint32_t f5x80; - uint8_t cu_enabled; - uint8_t compute_unit_count = 0; - - printk(BIOS_DEBUG, "NB: Function 5 Northbridge Control.. "); - - /* Determine the number of active compute units on this node */ - f5x80 = pci_read_config32(dev, 0x80); - cu_enabled = f5x80 & 0xf; - if (cu_enabled == 0x1) - compute_unit_count = 1; - if (cu_enabled == 0x3) - compute_unit_count = 2; - if (cu_enabled == 0x7) - compute_unit_count = 3; - if (cu_enabled == 0xf) - compute_unit_count = 4; - - /* Configure Processor TDP Running Average */ - dword = pci_read_config32(dev, 0xe0); - dword &= ~0xf; /* RunAvgRange = 0x9 */ - dword |= 0x9; - pci_write_config32(dev, 0xe0, dword); - - /* Configure northbridge P-states */ - dword = pci_read_config32(dev, 0x170); - dword &= ~(0x7 << 9); /* NbPstateThreshold = compute_unit_count */ - dword |= (compute_unit_count & 0x7) << 9; - pci_write_config32(dev, 0x170, dword); - - printk(BIOS_DEBUG, "done.\n"); -} - -static struct device_operations mcf5_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nb_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf5_driver_fam15_model10 __pci_driver = { - .ops = &mcf5_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1405, -}; - -static const struct pci_driver mcf5_driver_fam15 __pci_driver = { - .ops = &mcf5_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1605, -}; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c deleted file mode 100644 index df1d947cdb..0000000000 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ /dev/null @@ -1,1928 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * Copyright (C) 2015 - 2017 Timothy Pearson <tpearson@raptorengineering.com>, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci_ops.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/hypertransport.h> -#include <stdlib.h> -#include <string.h> -#include <lib.h> -#include <smbios.h> -#include <cpu/cpu.h> -#include <delay.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam10_sysconf.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/family_10h-family_15h/ram_calc.h> -#include <types.h> - -#if CONFIG(LOGICAL_CPUS) -#include <cpu/amd/multicore.h> -#include <pc80/mc146818rtc.h> -#endif - -#include "northbridge.h" -#include "amdfam10.h" -#include "ht_config.h" -#include "chip.h" - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -#include <cpu/amd/model_10xxx_rev.h> -#endif - -#if CONFIG(DIMM_DDR3) -#include "../amdmct/mct_ddr3/s3utils.h" -#endif - -struct amdfam10_sysconf_t sysconf; -u8 pirq_router_bus; - -#define FX_DEVS NODE_NUMS -static struct device *__f0_dev[FX_DEVS]; -struct device *__f1_dev[FX_DEVS]; -static struct device *__f2_dev[FX_DEVS]; -static struct device *__f4_dev[FX_DEVS]; -static unsigned int fx_devs = 0; - -struct device *get_node_pci(u32 nodeid, u32 fn) -{ -#if NODE_NUMS + CONFIG_CDB >= 32 - if ((CONFIG_CDB + nodeid) < 32) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); - } else { - return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); - } - -#else - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); -#endif -} - -static void get_fx_devs(void) -{ - int i; - for (i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } -} - -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned int reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -u32 amdfam10_nodeid(struct device *dev) -{ -#if NODE_NUMS == 64 - unsigned int busn; - busn = dev->bus->secondary; - if (busn != CONFIG_CBB) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; - } else { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; - } - -#else - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; -#endif -} - -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - val = 1 | (nodeid<<4) | (linkn<<12); - /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, - 0x3c0:0x3df */ - f1_write_config32(0xf4, val); - -} - -typedef enum { - HT_ROUTE_CLOSE, - HT_ROUTE_SCAN, - HT_ROUTE_FINAL, -} scan_state; - -static void ht_route_link(struct bus *link, scan_state mode) -{ - struct bus *parent = link->dev->bus; - u32 busses; - - if (mode == HT_ROUTE_SCAN) { - if (parent->subordinate == 0) - link->secondary = 0; - else - link->secondary = parent->subordinate + 1; - - link->subordinate = link->secondary; - } - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagated by the bridge if it is - * not correctly configured - */ - busses = pci_read_config32(link->dev, link->cap + 0x14); - busses &= ~(0xff << 8); - busses |= parent->secondary & 0xff; - if (mode == HT_ROUTE_CLOSE) - busses |= 0xff << 8; - else if (mode == HT_ROUTE_SCAN) - busses |= ((u32) link->secondary & 0xff) << 8; - else if (mode == HT_ROUTE_FINAL) - busses |= ((u32) link->secondary & 0xff) << 8; - pci_write_config32(link->dev, link->cap + 0x14, busses); - - if (mode == HT_ROUTE_FINAL) { - if (CONFIG(HT_CHAIN_DISTRIBUTE)) - parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1; - else - parent->subordinate = link->subordinate; - } -} - -static void amd_g34_fixup(struct bus *link, struct device *dev) -{ - uint32_t nodeid = amdfam10_nodeid(dev); - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - - if (cpuid_eax(0x80000001) >= 0x8) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d || is_fam15h()) { - f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); - - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - if (dual_node) { - /* Each G34 processor contains a defective HT link. - * See the BKDG Rev 3.62 section 2.7.1.5 for details. - */ - f3xe8 = pci_read_config32(get_node_pci(nodeid, 3), 0xe8); - uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30); - if (internal_node_number == 0) { - /* Node 0 */ - if (link->link_num == 6) /* Link 2 Sublink 1 */ - printk(BIOS_DEBUG, "amdfam10_scan_chain(): node %d (internal node ID %d): skipping defective HT link\n", nodeid, internal_node_number); - } else { - /* Node 1 */ - if (link->link_num == 5) /* Link 1 Sublink 1 */ - printk(BIOS_DEBUG, "amdfam10_scan_chain(): node %d (internal node ID %d): skipping defective HT link\n", nodeid, internal_node_number); - } - } - } -} - -static void amdfam10_scan_chain(struct bus *link) -{ - unsigned int next_unitid; - - /* See if there is an available configuration space mapping - * register in function 1. - */ - if (get_ht_c_index(link) >= 4) - return; - - /* Set up the primary, secondary and subordinate bus numbers. - * We have no idea how many busses are behind this bridge yet, - * so we set the subordinate bus number to 0xff for the moment. - */ - - ht_route_link(link, HT_ROUTE_SCAN); - - /* set the config map space */ - set_config_map_reg(link); - - /* Now we can scan all of the subordinate busses i.e. the - * chain on the hypertranport link - */ - - next_unitid = hypertransport_scan_chain(link); - - /* Now that nothing is overlapping it is safe to scan the children. */ - pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); - - ht_route_link(link, HT_ROUTE_FINAL); - - /* We know the number of busses behind this bridge. Set the - * subordinate bus number to it's real value - */ - if (0) { - /* Clear the extend reg. */ - clear_config_map_reg(link); - } - - set_config_map_reg(link); - - store_ht_c_conf_bus(link); -} - -/* Do sb ht chain at first, in case s2885 put sb chain - * (8131/8111) on link2, but put 8151 on link0. - */ -static void relocate_sb_ht_chain(void) -{ - struct device *dev; - struct bus *link, *prev = NULL; - u8 sblink; - - dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; - link = dev->link_list; - - while (link) { - if (link->link_num == sblink) { - if (!prev) - return; - prev->next = link->next; - link->next = dev->link_list; - dev->link_list = link; - return; - } - prev = link; - link = link->next; - } -} - -static void trim_ht_chain(struct device *dev) -{ - struct bus *link; - - /* Check for connected link. */ - for (link = dev->link_list; link; link = link->next) { - link->cap = 0x80 + (link->link_num * 0x20); - link->ht_link_up = ht_is_non_coherent_link(link); - } -} - -static void amdfam10_scan_chains(struct device *dev) -{ - struct bus *link; - -#if CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA) - if (is_fam15h()) { - uint8_t current_link_number = 0; - - for (link = dev->link_list; link; link = link->next) { - /* The following links have changed position in Fam15h G34 processors: - * Fam10 Fam15 - * Node 0 - * L3 --> L1 - * L0 --> L3 - * L1 --> L2 - * L2 --> L0 - * Node 1 - * L0 --> L0 - * L1 --> L3 - * L2 --> L1 - * L3 --> L2 - */ - if (link->link_num == 0) - link->link_num = 3; - else if (link->link_num == 1) - link->link_num = 2; - else if (link->link_num == 2) - link->link_num = 0; - else if (link->link_num == 3) - link->link_num = 1; - else if (link->link_num == 5) - link->link_num = 7; - else if (link->link_num == 6) - link->link_num = 5; - else if (link->link_num == 7) - link->link_num = 6; - - current_link_number++; - if (current_link_number > 3) - current_link_number = 0; - } - } -#endif - - /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ - trim_ht_chain(dev); - - for (link = dev->link_list; link; link = link->next) { - if (link->ht_link_up) { - if (CONFIG(CPU_AMD_MODEL_10XXX)) - amd_g34_fixup(link, dev); - amdfam10_scan_chain(link); - } - } -} - - -static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, - unsigned int goal_link) -{ - struct resource *res; - unsigned int nodeid, link = 0; - int result; - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - } - result = 2; - if (res) { - result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - return result; -} - -static struct resource *amdfam10_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xd8) { - reg = free_reg; // if no free, the free_reg still be 0 - } - - //Ext conf space - if (!reg) { - //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range - u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - - return resource; -} - -static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } - - //Ext conf space - if (!reg) { - //because of Extend conf space, we will never run out of reg, - // but we need one index to differ them. so same node and - // same link can have multi range - u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 - - } - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; -} - - -static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdfam10_find_iopair(dev, nodeid, link); - if (resource) { - u32 align; - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam10_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam10_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } -} - -static void amdfam10_read_resources(struct device *dev) -{ - u32 nodeid; - struct bus *link; - nodeid = amdfam10_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam10_link_read_bases(dev, nodeid, link->link_num); - } - } -} - -static void amdfam10_set_resource(struct device *dev, struct resource *resource, - u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); - } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes); // [39:8] - store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - -/** - * I tried to reuse the resource allocation code in amdfam10_set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - -static void amdfam10_create_vga_resource(struct device *dev, unsigned int nodeid) -{ - struct bus *link; - struct resource *res; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; - } - } - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); - set_vga_enable_reg(nodeid, link->link_num); - - /* Redirect VGA memory access to MMIO - * This signals the Family 10h resource parser - * to add a new MMIO mapping to the Range 11 - * MMIO control registers (starting at F1x1B8), - * and also reserves the resource in the E820 map. - */ - res = new_resource(dev, IOINDEX(0x1000 + 0x1b8, link->link_num)); - res->base = 0xa0000; - res->size = 0x20000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - amdfam10_set_resource(dev, res, nodeid); -} - -static void amdfam10_set_resources(struct device *dev) -{ - unsigned int nodeid; - struct bus *bus; - struct resource *res; - - /* Find the nodeid */ - nodeid = amdfam10_nodeid(dev); - - amdfam10_create_vga_resource(dev, nodeid); - - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - amdfam10_set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } -} - -static void mcf0_control_init(struct device *dev) -{ -} - -#if CONFIG(HAVE_ACPI_TABLES) -static const char *amdfam10_northbridge_acpi_name(const struct device *dev) -{ - return ""; -} -#endif - -static struct device_operations northbridge_operations = { - .read_resources = amdfam10_read_resources, - .set_resources = amdfam10_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = mcf0_control_init, - .scan_bus = amdfam10_scan_chains, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt_generator = northbridge_acpi_write_vars, - .acpi_name = amdfam10_northbridge_acpi_name, -#endif - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf0_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1200, -}; - -static void amdfam10_nb_init(void *chip_info) -{ - relocate_sb_ht_chain(); -} - -static const struct pci_driver mcf0_driver_fam15_model10 __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1400, -}; - -static const struct pci_driver mcf0_driver_fam15 __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1600, -}; - -struct chip_operations northbridge_amd_amdfam10_ops = { - CHIP_NAME("AMD Family 10h/15h Northbridge") - .enable_dev = 0, - .init = amdfam10_nb_init, -}; - -static void amdfam10_domain_read_resources(struct device *dev) -{ - unsigned int reg; - uint8_t nvram; - uint8_t enable_cc6; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); - - /* We have MMCONF_SUPPORT, create the resource window. */ - mmconf_resource(dev, MMIO_CONF_BASE); - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); - - if (is_fam15h()) { - enable_cc6 = 0; - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - enable_cc6 = !!nvram; - - if (enable_cc6) { - uint8_t node; - uint8_t interleaved; - int8_t range; - uint8_t max_node; - uint64_t max_range_limit; - uint32_t dword; - uint32_t dword2; - uint64_t qword; - uint8_t num_nodes; - - /* Find highest DRAM range (DramLimitAddr) */ - num_nodes = 0; - max_node = 0; - interleaved = 0; - max_range_limit = 0; - struct device *node_dev; - for (node = 0; node < FX_DEVS; node++) { - node_dev = get_node_pci(node, 0); - /* Test for node presence */ - if ((!node_dev) || (pci_read_config32(node_dev, PCI_VENDOR_ID) == 0xffffffff)) - continue; - - num_nodes++; - for (range = 0; range < 8; range++) { - dword = pci_read_config32(get_node_pci(node, 1), 0x40 + (range * 0x8)); - if (!(dword & 0x3)) - continue; - - if ((dword >> 8) & 0x7) - interleaved = 1; - - dword = pci_read_config32(get_node_pci(node, 1), 0x44 + (range * 0x8)); - dword2 = pci_read_config32(get_node_pci(node, 1), 0x144 + (range * 0x8)); - qword = 0xffffff; - qword |= ((((uint64_t)dword) >> 16) & 0xffff) << 24; - qword |= (((uint64_t)dword2) & 0xff) << 40; - - if (qword > max_range_limit) { - max_range_limit = qword; - max_node = dword & 0x7; - } - } - } - - /* Calculate CC6 storage area size */ - if (interleaved) - qword = (uint64_t)0x1000000 * num_nodes; - else - qword = 0x1000000; - - /* FIXME - * The BKDG appears to be incorrect as to the location of the CC6 save region - * lower boundary on non-interleaved systems, causing lockups on attempted write - * to the CC6 save region. - * - * For now, work around by allocating the maximum possible CC6 save region size. - * - * Determine if this is a BKDG error or a setup problem and remove this warning! - */ - qword = (0x1 << 27); - max_range_limit = (((uint64_t)(pci_read_config32(get_node_pci(max_node, 1), 0x124) & 0x1fffff)) << 27) - 1; - - printk(BIOS_INFO, "Reserving CC6 save segment base: %08llx size: %08llx\n", (max_range_limit + 1), qword); - - /* Reserve the CC6 save segment */ - reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10); - } - } -} - -static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) -{ - struct resource *min; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - -struct hw_mem_hole_info { - unsigned int hole_startk; - int node_id; -}; - -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - int i; - - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node - - hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole - } - } - - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id==-1) { - resource_t limitk_pri = 0; - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) continue; - - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k > 4 *1024 * 1024) break; // don't need to go to check - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G - mem_hole.node_id = i; - break; //only one hole - } - - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } - return mem_hole; -} - -#endif - -#include <cbmem.h> - -static void setup_uma_memory(void) -{ -#if CONFIG(GFXUMA) - uint32_t topmem = (uint32_t) bsp_topmem(); - uma_memory_size = get_uma_memory_size(topmem); - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - -static void amdfam10_domain_set_resources(struct device *dev) -{ - unsigned long mmio_basek; - u32 pci_tolm; - int i, idx; - struct bus *link; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; -#endif - - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -/* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - - mem_hole = get_hw_mem_hole_info(); - - // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - } - -#endif - - idx = 0x10; - for (i = 0; i < sysconf.nodes; i++) { - struct dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - - } - - /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned int pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, (idx | i), basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - - ram_resource(dev, (idx | i), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); - } - -#if CONFIG(GFXUMA) - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#endif - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } -} - -static void amdfam10_domain_scan_bus(struct device *dev) -{ - u32 reg; - int i; - struct bus *link; - /* Unmap all of the HT chains */ - for (reg = 0xe0; reg <= 0xec; reg += 4) { - f1_write_config32(reg, 0); - } - - for (link = dev->link_list; link; link = link->next) { - link->secondary = dev->bus->subordinate; - pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); - dev->bus->subordinate = link->subordinate; - } - - /* Tune the hypertransport transaction for best performance. - * Including enabling relaxed ordering if it is safe. - */ - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *f0_dev; - f0_dev = __f0_dev[i]; - if (f0_dev && f0_dev->enabled) { - u32 httc; - httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); - httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link_list->disable_relaxed_ordering) { - httc |= HTTC_RSP_PASS_PW; - } - printk(BIOS_SPEW, "%s passpw: %s\n", - dev_path(dev), - (!dev->link_list->disable_relaxed_ordering)? - "enabled":"disabled"); - pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); - } - } -} - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int amdfam10_get_smbios_data16(int *count, int handle, - unsigned long *current) -{ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info == NULL) - return 0; /* can't find amdmct information in cbmem */ - - struct device *dev = get_node_pci(0, 0); - struct northbridge_amd_amdfam10_config *config = dev->chip_info; - - int node; - int slot; - - struct smbios_type16 *t = (struct smbios_type16 *)*current; - int len = sizeof(struct smbios_type16); - - memset(t, 0, sizeof(struct smbios_type16)); - t->type = SMBIOS_PHYS_MEMORY_ARRAY; - t->handle = handle; - t->length = len - 2; - t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; - t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; - if ((mem_info->ecc_enabled) - && (mem_info->mct_stat.GStatus & (1 << GSB_ECCDIMMs)) - && !(mem_info->mct_stat.GStatus & (1 << GSB_DramECCDis))) - /* Single-bit ECC enabled */ - t->memory_error_correction = MEMORY_ARRAY_ECC_SINGLE_BIT; - t->maximum_capacity = config->maximum_memory_capacity / 1024; /* Convert to kilobytes */ - t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ - - t->number_of_memory_devices = 0; - /* Check all nodes for installed DIMMs */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) - /* Check all slots for installed DIMMs */ - for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) - if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) - /* Found an installed DIMM; increment count */ - t->number_of_memory_devices++; - - *current += len; - *count += 1; - return len; -} - -static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) -{ - if (is_fam15h()) { - if (CONFIG(DIMM_DDR3)) { - switch (speed) { - case 0x4: - return 333; - case 0x6: - return 400; - case 0xa: - return 533; - case 0xe: - return 667; - case 0x12: - return 800; - case 0x16: - return 933; - default: - return 0; - } - } else { - return 0; - } - } else { - if (CONFIG(DIMM_DDR2)) { - switch (speed) { - case 1: - return 200; - case 2: - return 266; - case 3: - return 333; - case 4: - return 400; - case 5: - return 533; - default: - return 0; - } - } else if (CONFIG(DIMM_DDR3)) { - switch (speed) { - case 3: - return 333; - case 4: - return 400; - case 5: - return 533; - case 6: - return 667; - case 7: - return 800; - default: - return 0; - } - } else { - return 0; - } - } -} - -static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, - unsigned long *current) -{ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); - if (mem_info == NULL) - return 0; /* can't find amdmct information in cbmem */ - - int single_len; - int len = 0; - int node; - int slot; - - /* Check all nodes for installed DIMMs */ - for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - /* Get configured RAM bus speed */ - uint16_t speed; - speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].Speed); - - /* Get maximum RAM bus speed */ - uint16_t max_speed; - max_speed = amdmct_mct_speed_enum_to_mhz(mem_info->dct_stat[node].DIMMAutoSpeed); - - /* Check all slots for installed DIMMs */ - for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { - if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { - /* Found an installed DIMM; populate tables */ - struct smbios_type17 *t = (struct smbios_type17 *)*current; - char string_buffer[256]; - - /* Initialize structure */ - memset(t, 0, sizeof(struct smbios_type17)); - - /* Calculate the total module size in bytes: - * Primary data width * 2^(#rows) * 2^(#cols) * #banks * #ranks - */ - uint8_t width, rows, cols, banks, ranks; - uint64_t chip_size; - uint32_t chip_width; - rows = mem_info->dct_stat[node].DimmRows[slot]; - cols = mem_info->dct_stat[node].DimmCols[slot]; - ranks = mem_info->dct_stat[node].DimmRanks[slot]; - banks = mem_info->dct_stat[node].DimmBanks[slot]; -#if CONFIG(DIMM_DDR3) - chip_size = mem_info->dct_stat[node].DimmChipSize[slot]; - chip_width = mem_info->dct_stat[node].DimmChipWidth[slot]; -#else - chip_size = 0; - chip_width = 0; -#endif - uint64_t dimm_size_bytes; - if (CONFIG(DIMM_DDR3)) { - width = mem_info->dct_stat[node].DimmWidth[slot]; - dimm_size_bytes = ((width / chip_width) * chip_size * ranks) / 8; - } else { - width = 8; - dimm_size_bytes = width * (1ULL << rows) * (1ULL << cols) * banks * ranks; - } - - memset(t, 0, sizeof(struct smbios_type17)); - t->type = SMBIOS_MEMORY_DEVICE; - t->handle = handle; - t->phys_memory_array_handle = parent_handle; - t->length = sizeof(struct smbios_type17) - 2; - if (dimm_size_bytes > 0x800000000) { - t->size = 0x7FFF; - t->extended_size = dimm_size_bytes >> 16; - } else { - t->size = dimm_size_bytes / (1024*1024); - t->size &= (~0x8000); /* size specified in megabytes */ - } - t->total_width = t->data_width = 64; - if (mem_info->dct_stat[node].DimmECCPresent & (1 << slot)) - t->total_width += 8; - t->attributes = 0; - t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 4 bits of the attributes field */ - t->form_factor = MEMORY_FORMFACTOR_DIMM; - if (mem_info->dct_stat[node].Dual_Node_Package) { - snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node >> 1, - (mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1); - } else { - snprintf(string_buffer, sizeof(string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); - } - t->device_locator = smbios_add_string(t->eos, string_buffer); - if (CONFIG(DIMM_DDR2)) - t->memory_type = MEMORY_TYPE_DDR2; - else if (CONFIG(DIMM_DDR3)) - t->memory_type = MEMORY_TYPE_DDR3; - t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; - if (mem_info->dct_stat[node].DimmRegistered[slot]) - t->type_detail |= MEMORY_TYPE_DETAIL_REGISTERED; - else - t->type_detail |= MEMORY_TYPE_DETAIL_UNBUFFERED; - t->speed = max_speed; - t->clock_speed = speed; - smbios_fill_dimm_manufacturer_from_id(mem_info->dct_stat[node].DimmManufacturerID[slot], t); - t->part_number = smbios_add_string(t->eos, mem_info->dct_stat[node].DimmPartNumber[slot]); - if (mem_info->dct_stat[node].DimmSerialNumber[slot] == 0) { - t->serial_number = smbios_add_string(t->eos, "None"); - } else { - snprintf(string_buffer, sizeof(string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); - t->serial_number = smbios_add_string(t->eos, string_buffer); - } - if (CONFIG(DIMM_DDR2)) { - /* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */ - t->minimum_voltage = 1800; - t->maximum_voltage = 1800; - t->configured_voltage = 1800; - } else if (CONFIG(DIMM_DDR3)) { -#if CONFIG(DIMM_DDR3) - /* Find the maximum and minimum supported voltages */ - uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot]; - uint8_t configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot]; - - if (supported_voltages & 0x8) - t->minimum_voltage = 1150; - else if (supported_voltages & 0x4) - t->minimum_voltage = 1250; - else if (supported_voltages & 0x2) - t->minimum_voltage = 1350; - else if (supported_voltages & 0x1) - t->minimum_voltage = 1500; - - if (supported_voltages & 0x1) - t->maximum_voltage = 1500; - else if (supported_voltages & 0x2) - t->maximum_voltage = 1350; - else if (supported_voltages & 0x4) - t->maximum_voltage = 1250; - else if (supported_voltages & 0x8) - t->maximum_voltage = 1150; - - if (configured_voltage & 0x8) - t->configured_voltage = 1150; - else if (configured_voltage & 0x4) - t->configured_voltage = 1250; - else if (configured_voltage & 0x2) - t->configured_voltage = 1350; - else if (configured_voltage & 0x1) - t->configured_voltage = 1500; -#endif - } - t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ - single_len = t->length + smbios_string_table_len(t->eos); - len += single_len; - *current += single_len; - handle++; - *count += 1; - } - } - } - - return len; -} - -static int amdfam10_get_smbios_data(struct device *dev, int *handle, unsigned long *current) -{ - int len; - int count = 0; - len = amdfam10_get_smbios_data16(&count, *handle, current); - len += amdfam10_get_smbios_data17(&count, *handle + 1, *handle, current); - *handle += count; - return len; -} -#endif - -#if CONFIG(HAVE_ACPI_TABLES) -static const char *amdfam10_domain_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - return NULL; -} -#endif - -static struct device_operations pci_domain_ops = { - .read_resources = amdfam10_domain_read_resources, - .set_resources = amdfam10_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = amdfam10_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = amdfam10_domain_acpi_name, -#endif -#if CONFIG(GENERATE_SMBIOS_TABLES) - .get_smbios_data = amdfam10_get_smbios_data, -#endif -}; - -static void sysconf_init(struct device *dev) // first node -{ - sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - sysconf.segbit = 0; - sysconf.ht_c_num = 0; - - unsigned int ht_c_index; - - for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { - sysconf.ht_c_conf_bus[ht_c_index] = 0; - } - - sysconf.nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - sysconf.nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); -#endif - - sysconf.enabled_apic_ext_id = 0; - sysconf.lift_bsp_apicid = 0; - - /* Find the bootstrap processors apicid */ - sysconf.bsp_apicid = lapicid(); - sysconf.apicid_offset = sysconf.bsp_apicid; - -#if CONFIG(ENABLE_APIC_EXT_ID) - if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) - { - sysconf.enabled_apic_ext_id = 1; - } - #if (CONFIG_APIC_ID_OFFSET > 0) - if (sysconf.enabled_apic_ext_id) { - if (sysconf.bsp_apicid == 0) { - /* bsp apic id is not changed */ - sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; - } else { - sysconf.lift_bsp_apicid = 1; - } - } - #endif -#endif -} - -static void remap_bsp_lapic(struct bus *cpu_bus) -{ - struct device_path cpu_path; - struct device *cpu; - u32 bsp_lapic_id = lapicid(); - - if (bsp_lapic_id) { - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = 0; - cpu = find_dev_path(cpu_bus, &cpu_path); - if (cpu) - cpu->path.apic.apic_id = bsp_lapic_id; - } -} - -static void cpu_bus_scan(struct device *dev) -{ - struct bus *cpu_bus; - struct device *dev_mc; -#if CONFIG_CBB - struct device *pci_domain; -#endif - int nvram = 0; - int i,j; - int nodes; - unsigned int nb_cfg_54; - unsigned int siblings; - int cores_found; - int disable_siblings; - uint8_t disable_cu_siblings = 0; - unsigned int ApicIdCoreIdSize; - - nb_cfg_54 = 0; - ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); - if (ApicIdCoreIdSize) { - siblings = (1<<ApicIdCoreIdSize)-1; - } else { - siblings = 3; //quad core - } - - disable_siblings = !CONFIG(LOGICAL_CPUS); -#if CONFIG(LOGICAL_CPUS) - get_option(&disable_siblings, "multi_core"); -#endif - - // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp??? - nb_cfg_54 = read_nb_cfg_54(); - -#if CONFIG_CBB - dev_mc = pcidev_on_root(CONFIG_CDB, 0); //0x00 - if (dev_mc && dev_mc->bus) { - printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); - pci_domain = dev_mc->bus->dev; - if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { - printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff - printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); - - } else { - printk(BIOS_DEBUG, " but it is not under pci_domain directly "); - } - printk(BIOS_DEBUG, "\n"); - } - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - dev_mc = pcidev_on_root(0x18, 0); - if (dev_mc && dev_mc->bus) { - printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); - pci_domain = dev_mc->bus->dev; - if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { - if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { - printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff - printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - while (dev_mc) { - printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); - dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); - printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); - dev_mc = dev_mc->sibling; - } - } - } - } - } - -#endif - - dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); - if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); - die(""); - } - - sysconf_init(dev_mc); - - nodes = sysconf.nodes; - -#if CONFIG_CBB && (NODE_NUMS > 32) - if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe - if (pci_domain->link_list && !pci_domain->link_list->next) { - struct bus *new_link = new_link(pci_domain); - pci_domain->link_list->next = new_link; - new_link->link_num = 1; - new_link->dev = pci_domain; - new_link->children = 0; - printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); - } - pci_domain->link_list->next->secondary = CONFIG_CBB - 1; - } -#endif - /* Find which cpus are present */ - cpu_bus = dev->link_list; - - /* Always use the devicetree node with lapic_id 0 for BSP. */ - remap_bsp_lapic(cpu_bus); - - if (get_option(&nvram, "compute_unit_siblings") == CB_SUCCESS) - disable_cu_siblings = !!nvram; - - if (disable_cu_siblings) - printk(BIOS_DEBUG, "Disabling siblings on each compute unit as requested\n"); - - for (i = 0; i < nodes; i++) { - struct device *cdb_dev; - unsigned int busn, devn; - struct bus *pbus; - - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint8_t dual_node = 0; - uint32_t f3xe8; - uint32_t model; - - busn = CONFIG_CBB; - devn = CONFIG_CDB+i; - pbus = dev_mc->bus; -#if CONFIG_CBB && (NODE_NUMS > 32) - if (i >= 32) { - busn--; - devn-=32; - pbus = pci_domain->link_list->next; - } -#endif - - /* Find the cpu's pci device */ - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - } - - - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - if (cdb_dev) - add_more_links(cdb_dev, 4); - - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 4)); - if (cdb_dev) - add_more_links(cdb_dev, 4); - - f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); - - model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - - if (is_fam15h()) { - /* Family 15h or later */ - fam15h = 1; - nb_cfg_54 = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d) - /* Check for dual node capability */ - if (f3xe8 & 0x20000000) - dual_node = 1; - - cores_found = 0; // one core - if (fam15h) - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); - else - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); - int enable_node = cdb_dev && cdb_dev->enabled; - if (enable_node) { - if (fam15h) { - cores_found = pci_read_config32(cdb_dev, 0x84) & 0xff; - } else { - j = pci_read_config32(cdb_dev, 0xe8); - cores_found = (j >> 12) & 3; // dev is func 3 - if (siblings > 3) - cores_found |= (j >> 13) & 4; - } - printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found); - } - - if (siblings > cores_found) - siblings = cores_found; - - u32 jj; - if (disable_siblings) { - jj = 0; - } else - { - jj = cores_found; - } - - for (j = 0; j <=jj; j++) { - u32 apic_id; - - if (dual_node) { - apic_id = 0; - if (fam15h) { - apic_id |= ((i >> 1) & 0x3) << 5; /* Node ID */ - apic_id |= ((i & 0x1) * (siblings + 1)) + j; /* Core ID */ - } else { - if (nb_cfg_54) { - apic_id |= ((i >> 1) & 0x3) << 4; /* Node ID */ - apic_id |= ((i & 0x1) * (siblings + 1)) + j; /* Core ID */ - } else { - apic_id |= i & 0x3; /* Node ID */ - apic_id |= (((i & 0x1) * (siblings + 1)) + j) << 4; /* Core ID */ - } - } - } else { - if (fam15h) { - apic_id = 0; - apic_id |= (i & 0x7) << 4; /* Node ID */ - apic_id |= j & 0xf; /* Core ID */ - } else { - apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - } - } - -#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0) - if (sysconf.enabled_apic_ext_id) { - if (apic_id != 0 || sysconf.lift_bsp_apicid) { - apic_id += sysconf.apicid_offset; - } - } -#endif - if (disable_cu_siblings && (j & 0x1)) - continue; - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } - } -} - -static void detect_and_enable_probe_filter(struct device *dev) -{ - uint32_t dword; - - uint8_t nvram; - uint8_t enable_probe_filter; - - /* Check to see if the probe filter is allowed */ - enable_probe_filter = 1; - if (get_option(&nvram, "probe_filter") == CB_SUCCESS) - enable_probe_filter = !!nvram; - - if (!enable_probe_filter) - return; - - uint8_t fam15h = 0; - uint8_t rev_gte_d = 0; - uint32_t model; - - model = cpuid_eax(0x80000001); - model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); - - if (is_fam15h()) { - /* Family 15h or later */ - fam15h = 1; - } - - if ((model >= 0x8) || fam15h) - /* Revision D or later */ - rev_gte_d = 1; - - if (rev_gte_d && (sysconf.nodes > 1)) { - /* Enable the probe filter */ - uint8_t i; - uint8_t pfmode = 0x0; - - uint32_t f3x58[MAX_NODES_SUPPORTED]; - uint32_t f3x5c[MAX_NODES_SUPPORTED]; - - printk(BIOS_DEBUG, "Enabling probe filter\n"); - - /* Disable L3 and DRAM scrubbers and configure system for probe filter support */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f2x_dev = pcidev_on_root(0x18 + i, 2); - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - - f3x58[i] = pci_read_config32(f3x_dev, 0x58); - f3x5c[i] = pci_read_config32(f3x_dev, 0x5c); - pci_write_config32(f3x_dev, 0x58, f3x58[i] & ~((0x1f << 24) | 0x1f)); - pci_write_config32(f3x_dev, 0x5c, f3x5c[i] & ~0x1); - - dword = pci_read_config32(f2x_dev, 0x1b0); - dword &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x0 */ - pci_write_config32(f2x_dev, 0x1b0, dword); - - msr_t msr = rdmsr_amd(BU_CFG2_MSR); - msr.hi |= 1 << (42 - 32); - wrmsr_amd(BU_CFG2_MSR, msr); - - if (is_fam15h()) { - uint8_t subcache_size = 0x0; - uint8_t pref_so_repl = 0x0; - uint32_t f3x1c4 = pci_read_config32(f3x_dev, 0x1c4); - if ((f3x1c4 & 0xffff) == 0xcccc) { - subcache_size = 0x1; - pref_so_repl = 0x2; - pfmode = 0x3; - } else { - pfmode = 0x2; - } - - dword = pci_read_config32(f3x_dev, 0x1d4); - dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ - dword &= ~(0x3 << 20); /* PFPreferredSORepl = pref_so_repl */ - dword |= (pref_so_repl & 0x3) << 20; - dword |= 0x1 << 17; /* PFWayHashEn = 0x1 */ - dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ - dword &= ~(0x3 << 10); /* PFSubCacheSize3 = subcache_size */ - dword |= (subcache_size & 0x3) << 10; - dword &= ~(0x3 << 8); /* PFSubCacheSize2 = subcache_size */ - dword |= (subcache_size & 0x3) << 8; - dword &= ~(0x3 << 6); /* PFSubCacheSize1 = subcache_size */ - dword |= (subcache_size & 0x3) << 6; - dword &= ~(0x3 << 4); /* PFSubCacheSize0 = subcache_size */ - dword |= (subcache_size & 0x3) << 4; - dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ - dword |= 0x2 << 2; - pci_write_config32(f3x_dev, 0x1d4, dword); - } else { - pfmode = 0x2; - - dword = pci_read_config32(f3x_dev, 0x1d4); - dword |= 0x1 << 29; /* PFLoIndexHashEn = 0x1 */ - dword &= ~(0x3 << 20); /* PFPreferredSORepl = 0x2 */ - dword |= 0x2 << 20; - dword |= 0xf << 12; /* PFSubCacheEn = 0xf */ - dword &= ~(0x3 << 10); /* PFSubCacheSize3 = 0x0 */ - dword &= ~(0x3 << 8); /* PFSubCacheSize2 = 0x0 */ - dword &= ~(0x3 << 6); /* PFSubCacheSize1 = 0x0 */ - dword &= ~(0x3 << 4); /* PFSubCacheSize0 = 0x0 */ - dword &= ~(0x3 << 2); /* PFWayNum = 0x2 */ - dword |= 0x2 << 2; - pci_write_config32(f3x_dev, 0x1d4, dword); - } - } - - udelay(40); - - disable_cache(); - wbinvd(); - - /* Enable probe filter */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - - dword = pci_read_config32(f3x_dev, 0x1c4); - dword |= (0x1 << 31); /* L3TagInit = 1 */ - pci_write_config32(f3x_dev, 0x1c4, dword); - do { - } while (pci_read_config32(f3x_dev, 0x1c4) & (0x1 << 31)); - - dword = pci_read_config32(f3x_dev, 0x1d4); - dword &= ~0x3; /* PFMode = pfmode */ - dword |= pfmode & 0x3; - pci_write_config32(f3x_dev, 0x1d4, dword); - do { - } while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19))); - } - - if (is_fam15h()) { - printk(BIOS_DEBUG, "Enabling ATM mode\n"); - - /* Enable ATM mode */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f0x_dev = - pcidev_on_root(0x18 + i, 0); - struct device *f3x_dev = - pcidev_on_root(0x18 + i, 3); - - dword = pci_read_config32(f0x_dev, 0x68); - dword |= (0x1 << 12); /* ATMModeEn = 1 */ - pci_write_config32(f0x_dev, 0x68, dword); - - dword = pci_read_config32(f3x_dev, 0x1b8); - dword |= (0x1 << 27); /* L3ATMModeEn = 1 */ - pci_write_config32(f3x_dev, 0x1b8, dword); - } - } - - enable_cache(); - - /* Reenable L3 and DRAM scrubbers */ - for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - - pci_write_config32(f3x_dev, 0x58, f3x58[i]); - pci_write_config32(f3x_dev, 0x5c, f3x5c[i]); - } - - } -} - -static void detect_and_enable_cache_partitioning(struct device *dev) -{ - uint8_t i; - uint32_t dword; - - uint8_t nvram; - uint8_t enable_l3_cache_partitioning; - - /* Check to see if cache partitioning is allowed */ - enable_l3_cache_partitioning = 0; - if (get_option(&nvram, "l3_cache_partitioning") == CB_SUCCESS) - enable_l3_cache_partitioning = !!nvram; - - if (!enable_l3_cache_partitioning) - return; - - if (is_fam15h()) { - printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n"); - - uint32_t f5x80; - uint8_t cu_enabled; - uint8_t compute_unit_count = 0; - - for (i = 0; i < sysconf.nodes; i++) { - struct device *f3x_dev = pcidev_on_root(0x18 + i, 3); - struct device *f4x_dev = pcidev_on_root(0x18 + i, 4); - struct device *f5x_dev = pcidev_on_root(0x18 + i, 5); - - /* Determine the number of active compute units on this node */ - f5x80 = pci_read_config32(f5x_dev, 0x80); - cu_enabled = f5x80 & 0xf; - if (cu_enabled == 0x1) - compute_unit_count = 1; - if (cu_enabled == 0x3) - compute_unit_count = 2; - if (cu_enabled == 0x7) - compute_unit_count = 3; - if (cu_enabled == 0xf) - compute_unit_count = 4; - - /* Disable BAN mode */ - dword = pci_read_config32(f3x_dev, 0x1b8); - dword &= ~(0x7 << 19); /* L3BanMode = 0x0 */ - pci_write_config32(f3x_dev, 0x1b8, dword); - - /* Set up cache mapping */ - dword = pci_read_config32(f4x_dev, 0x1d4); - if (compute_unit_count == 1) { - dword |= 0xf; /* ComputeUnit0SubCacheEn = 0xf */ - } - if (compute_unit_count == 2) { - dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0xc */ - dword |= (0xc << 4); - dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x3 */ - dword |= 0x3; - } - if (compute_unit_count == 3) { - dword &= ~(0xf << 8); /* ComputeUnit2SubCacheEn = 0x8 */ - dword |= (0x8 << 8); - dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0x4 */ - dword |= (0x4 << 4); - dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x3 */ - dword |= 0x3; - } - if (compute_unit_count == 4) { - dword &= ~(0xf << 12); /* ComputeUnit3SubCacheEn = 0x8 */ - dword |= (0x8 << 12); - dword &= ~(0xf << 8); /* ComputeUnit2SubCacheEn = 0x4 */ - dword |= (0x4 << 8); - dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0x2 */ - dword |= (0x2 << 4); - dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x1 */ - dword |= 0x1; - } - pci_write_config32(f4x_dev, 0x1d4, dword); - - /* Enable cache partitioning */ - pci_write_config32(f4x_dev, 0x1d4, dword); - if (compute_unit_count == 1) { - dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x1 */ - dword |= (0x1 << 26); - } else if (compute_unit_count == 2) { - dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x3 */ - dword |= (0x3 << 26); - } else if (compute_unit_count == 3) { - dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x7 */ - dword |= (0x7 << 26); - } else if (compute_unit_count == 4) { - dword |= (0xf << 26); /* MaskUpdateForComputeUnit = 0xf */ - } - pci_write_config32(f4x_dev, 0x1d4, dword); - } - } -} - -static void cpu_bus_init(struct device *dev) -{ - detect_and_enable_probe_filter(dev); - detect_and_enable_cache_partitioning(dev); - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, -}; - -static void root_complex_enable_dev(struct device *dev) -{ - static int done = 0; - - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ - if (!done) { - setup_bsp_ramtop(); - setup_uma_memory(); - done = 1; - } - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -static void root_complex_finalize(void *chip_info) { -#if CONFIG(HAVE_ACPI_RESUME) && CONFIG(DIMM_DDR3) - save_mct_information_to_nvram(); -#endif -} - -struct chip_operations northbridge_amd_amdfam10_root_complex_ops = { - CHIP_NAME("AMD Family 10h/15h Root Complex") - .enable_dev = root_complex_enable_dev, - .final = root_complex_finalize, -}; diff --git a/src/northbridge/amd/amdfam10/northbridge.h b/src/northbridge/amd/amdfam10/northbridge.h deleted file mode 100644 index fdfd4c8c2c..0000000000 --- a/src/northbridge/amd/amdfam10/northbridge.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_AMD_AMDFAM10_H -#define NORTHBRIDGE_AMD_AMDFAM10_H - -u32 amdfam10_scan_root_bus(struct device *root, u32 max); - -#endif /* NORTHBRIDGE_AMD_AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h deleted file mode 100644 index 771ef12b95..0000000000 --- a/src/northbridge/amd/amdfam10/nums.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_NUMS_H - -#define AMDFAM10_NUMS_H - -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - #if CONFIG_MAX_PHYSICAL_CPUS > 32 - #define NODE_NUMS 64 - #else - #define NODE_NUMS 32 - #endif -#else - #define NODE_NUMS 8 -#endif - -// max HC installed at the same time. ...could be bigger than (48+24) if we have 3x4x4 -#define HC_NUMS 32 - -//it could be more bigger -#define HC_POSSIBLE_NUM 32 - -#endif diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c deleted file mode 100644 index 410923a01e..0000000000 --- a/src/northbridge/amd/amdfam10/pci.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include "pci.h" - -/* bit [10,8] are dev func, bit[1,0] are dev index */ - -u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) -{ - u32 dword; - - pci_write_config32(dev, index_reg, index); - dword = pci_read_config32(dev, index_reg+0x4); - return dword; -} - -#ifdef UNUSED_CODE -void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, - u32 data) -{ - - pci_write_config32(dev, index_reg, index); - - pci_write_config32(dev, index_reg + 0x4, data); - -} -#endif - -u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, - u32 index) -{ - - u32 dword; - - index &= ~(1<<30); - pci_write_config32(dev, index_reg, index); - do { - dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); - dword = pci_read_config32(dev, index_reg+0x4); - return dword; -} - -#ifdef UNUSED_CODE -void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, - u32 index, u32 data) -{ - - u32 dword; - - pci_write_config32(dev, index_reg + 0x4, data); - index |= (1<<30); - pci_write_config32(dev, index_reg, index); - do { - dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); - -} -#endif diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h deleted file mode 100644 index 21623c1168..0000000000 --- a/src/northbridge/amd/amdfam10/pci.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_PCI_H -#define AMDFAM10_PCI_H - -#include <stdint.h> -#include <device/pci_type.h> -#include <device/pci_def.h> - -u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index); -u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index); - -#endif diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h deleted file mode 100644 index c9c57ff2c2..0000000000 --- a/src/northbridge/amd/amdfam10/raminit.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AMDFAM10_RAMINIT_H -#define AMDFAM10_RAMINIT_H - -#include <device/pci.h> -#include <northbridge/amd/amdmct/amddefs.h> -#include <northbridge/amd/amdmct/wrappers/mcti.h> - -struct sys_info; -struct DCTStatStruc; -struct MCTStatStruc; - -void activate_spd_rom(const struct mem_controller *ctrl); - -int mctRead_SPD(u32 smaddr, u32 reg); -void mctSMBhub_Init(u32 node); -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); -void set_sysinfo_in_ram(u32 val); -struct sys_info *get_sysinfo(void); -void raminit_amdmct(struct sys_info *sysinfo); -void amdmct_cbmem_store_info(struct sys_info *sysinfo); -void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); -uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq); -u8 mctGetProcessorPackageType(void); -void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val); -uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg); -uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index); -void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data); -void fam15h_switch_dct(uint32_t dev, uint8_t dct); -uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg); -void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val); - -#endif diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c deleted file mode 100644 index a25a1510c8..0000000000 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <device/pci.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <northbridge/amd/amdfam10/debug.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> -#include <timestamp.h> - -/* Global allocation of sysinfo_car */ -#include <arch/early_variables.h> -static struct sys_info sysinfo_car CAR_GLOBAL; - -struct sys_info *get_sysinfo(void) -{ - return car_get_var_ptr(&sysinfo_car); -} - -struct mem_controller; -extern int spd_read_byte(unsigned int device, unsigned int address); - -void __weak activate_spd_rom(const struct mem_controller *ctrl) -{ -} - -void fam15h_switch_dct(uint32_t dev, uint8_t dct) -{ - uint32_t dword; - - dword = Get_NB32(dev, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - Set_NB32(dev, 0x10c, dword); -} - -static inline void fam15h_switch_nb_pstate_config_reg(uint32_t dev, uint8_t nb_pstate) -{ - uint32_t dword; - - dword = Get_NB32(dev, 0x10c); - dword &= ~(0x3 << 4); - dword |= (nb_pstate & 0x3) << 4; - Set_NB32(dev, 0x10c, dword); -} - -uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - return Get_NB32(dev, reg); - } else { - return Get_NB32(dev, (0x100 * dct) + reg); - } -} - -void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - Set_NB32(dev, reg, val); - } else { - Set_NB32(dev, (0x100 * dct) + reg, val); - } -} - -uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - fam15h_switch_nb_pstate_config_reg(dev_map, nb_pstate); - return Get_NB32(dev, reg); - } else { - return Get_NB32(dev, (0x100 * dct) + reg); - } -} - -void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - fam15h_switch_nb_pstate_config_reg(dev_map, nb_pstate); - Set_NB32(dev, reg, val); - } else { - Set_NB32(dev, (0x100 * dct) + reg, val); - } -} - -uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - return Get_NB32_index_wait(dev, index_reg, index); - } else { - return Get_NB32_index_wait(dev, (0x100 * dct) + index_reg, index); - } -} - -void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data) -{ - if (is_fam15h()) { - /* Obtain address of function 0x1 */ - uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12); - fam15h_switch_dct(dev_map, dct); - Set_NB32_index_wait(dev, index_reg, index, data); - } else { - Set_NB32_index_wait(dev, (0x100 * dct) + index_reg, index, data); - } -} - -static uint16_t voltage_index_to_mv(uint8_t index) -{ - if (index & 0x8) - return 1150; - if (index & 0x4) - return 1250; - else if (index & 0x2) - return 1350; - else - return 1500; -} - -uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) -{ - /* FIXME - * Mainboards need to be able to specify the maximum number of DIMMs installable per channel - * For now assume a maximum of 2 DIMMs per channel can be installed - */ - uint8_t MaxDimmsInstallable = 2; - - /* Return limited maximum RAM frequency */ - if (CONFIG(DIMM_DDR2)) { - if (CONFIG(DIMM_REGISTERED) && registered) { - /* K10 BKDG Rev. 3.62 Table 53 */ - if (count > 2) { - /* Limit to DDR2-533 */ - if (freq > 266) { - freq = 266; - print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n"); - } - } - } else { - /* K10 BKDG Rev. 3.62 Table 52 */ - if (count > 1) { - /* Limit to DDR2-800 */ - if (freq > 400) { - freq = 400; - print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n"); - } - } - } - } else if (CONFIG(DIMM_DDR3)) { - if (voltage == 0) { - printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__); - voltage = 0x1; - } - - if (is_fam15h()) { - if (CONFIG_CPU_SOCKET_TYPE == 0x15) { - /* Socket G34 */ - if (CONFIG(DIMM_REGISTERED) && registered) { - /* Fam15h BKDG Rev. 3.14 Table 27 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (count > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - /* 1.50V */ - if (count > 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1866 */ - if (freq > 933) { - freq = 933; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } else { - /* Fam15h BKDG Rev. 3.14 Table 26 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (MaxDimmsInstallable > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - if (MaxDimmsInstallable == 1) { - if (count > 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1866 */ - if (freq > 933) { - freq = 933; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - } - } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) { - /* Socket C32 */ - if (CONFIG(DIMM_REGISTERED) && registered) { - /* Fam15h BKDG Rev. 3.14 Table 30 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (count > 1) { - if (highest_rank_count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - /* 1.50V */ - if (count > 1) { - if (highest_rank_count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - if (highest_rank_count > 2) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - } else { - /* Fam15h BKDG Rev. 3.14 Table 29 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - if (MaxDimmsInstallable == 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - } - } else { - /* TODO - * Other socket support unimplemented - */ - } - } else { - if (CONFIG(DIMM_REGISTERED) && registered) { - /* K10 BKDG Rev. 3.62 Table 34 */ - if (count > 2) { - /* Limit to DDR3-800 */ - if (freq > 400) { - freq = 400; - printk(BIOS_DEBUG, "%s: More than 2 registered DIMMs on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); - } - } else if (count == 2) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: 2 registered DIMMs on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else { - /* K10 BKDG Rev. 3.62 Table 33 */ - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: unbuffered DIMMs on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } - } - - return freq; -} - -int mctRead_SPD(u32 smaddr, u32 reg) -{ - return spd_read_byte(smaddr, reg); -} - - -void mctSMBhub_Init(u32 node) -{ - struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &(sysinfo->ctrl[node]); - activate_spd_rom(ctrl); -} - - -void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) -{ - int j; - struct sys_info *sysinfo = &sysinfo_car; - struct mem_controller *ctrl = &(sysinfo->ctrl[node]); - - for (j = 0; j < DIMM_SOCKETS; j++) { - pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff; - pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff; - } - -} - -#if CONFIG(SET_FIDVID) -u8 mctGetProcessorPackageType(void) { - /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ - u32 BrandId = cpuid_ebx(0x80000001); - return (u8)((BrandId >> 28) & 0x0F); -} -#endif - -void raminit_amdmct(struct sys_info *sysinfo) -{ - struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); - struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; - - printk(BIOS_DEBUG, "raminit_amdmct begin:\n"); - timestamp_add_now(TS_BEFORE_INITRAM); - - mctAutoInitMCT_D(pMCTstat, pDCTstatA); - - timestamp_add_now(TS_AFTER_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct end:\n"); -} - -void amdmct_cbmem_store_info(struct sys_info *sysinfo) -{ - if (!sysinfo) - return; - - /* Save memory info structures for use in ramstage */ - size_t i; - struct DCTStatStruc *pDCTstatA = NULL; - - if (!acpi_is_wakeup_s3()) { - /* Allocate memory */ - struct amdmct_memory_info *mem_info; - mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); - if (!mem_info) - return; - - printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__); - - /* Initialize memory */ - memset(mem_info, 0, sizeof(struct amdmct_memory_info)); - - /* Copy data */ - memcpy(&mem_info->mct_stat, &sysinfo->MCTstat, sizeof(struct MCTStatStruc)); - for (i = 0; i < MAX_NODES_SUPPORTED; i++) { - pDCTstatA = sysinfo->DCTstatA + i; - memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); - } - mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); - mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); - - /* Zero out invalid/unused pointers */ -#if CONFIG(DIMM_DDR3) - for (i = 0; i < MAX_NODES_SUPPORTED; i++) { - mem_info->dct_stat[i].C_MCTPtr = NULL; - mem_info->dct_stat[i].C_DCTPtr[0] = NULL; - mem_info->dct_stat[i].C_DCTPtr[1] = NULL; - } -#endif - } -} diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c deleted file mode 100644 index 218df75887..0000000000 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> -#include <delay.h> - -static void set_htic_bit(u8 i, u32 val, u8 bit) -{ - u32 dword; - dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); - dword &= ~(1<<bit); - dword |= ((val & 1) <<bit); - pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); -} - -#ifdef UNUSED_CODE -static u32 get_htic_bit(u8 i, u8 bit) -{ - u32 dword; - dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); - dword &= (1<<bit); - return dword; -} - -static void wait_till_sysinfo_in_ram(void) -{ - while (1) { - /* give the NB a break, many CPUs spinning on one bit makes a - * lot of traffic and time is not too important to APs. - */ - udelay(1000); - if (get_htic_bit(0, 9)) return; - } -} -#endif - -void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr) -{ - int i; - int j; - int index = 0; - struct mem_controller *ctrl; - for (i = 0; i < controllers; i++) { - ctrl = &ctrl_a[i]; - ctrl->node_id = i; - ctrl->f0 = NODE_PCI(i, 0); - ctrl->f1 = NODE_PCI(i, 1); - ctrl->f2 = NODE_PCI(i, 2); - ctrl->f3 = NODE_PCI(i, 3); - ctrl->f4 = NODE_PCI(i, 4); - ctrl->f5 = NODE_PCI(i, 5); - - if (spd_addr == (void *)0) continue; - - ctrl->spd_switch_addr = spd_addr[index++]; - - for (j = 0; j < 8; j++) { - ctrl->spd_addr[j] = spd_addr[index++]; - - } - } -} - -void set_sysinfo_in_ram(u32 val) -{ - set_htic_bit(0, val, 9); -} diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c deleted file mode 100644 index 76d1144e7d..0000000000 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/lapic.h> -#include <device/pci_ops.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> - -/* mmconf is not ready */ -/* io_ext is not ready */ -u32 cpu_init_detected(u8 nodeid) -{ - u32 htic; - pci_devfn_t dev; - - dev = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(dev, HT_INIT_CONTROL); - - return !!(htic & HTIC_INIT_Detect); -} - -u32 bios_reset_detected(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); - - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -u32 cold_reset_detected(void) -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); - - return !(htic & HTIC_ColdR_Detect); -} - -u32 other_reset_detected(void) // other warm reset not started by BIOS -{ - u32 htic; - htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); - - return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); -} - -void distinguish_cpu_resets(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_io_write_config32(device, HT_INIT_CONTROL, htic); -} - -u32 warm_reset_detect(u8 nodeid) -{ - u32 htic; - pci_devfn_t device; - device = NODE_PCI(nodeid, 0); - htic = pci_io_read_config32(device, HT_INIT_CONTROL); - return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); -} - -void set_bios_reset(void) -{ - - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i,0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - - -/* Look up a which bus a given node/link combination is on. - * return 0 when we can't find the answer. - */ -static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three bit -{ - u32 reg; - u32 val; - - // put node and link in correct bit - val = ((node & 0x0f)<<4) | ((node & 0x30)<< (12-4)) | ((link & 0x07)<<8); - - for (reg = 0xE0; reg < 0xF0; reg += 0x04) { - u32 config_map; - config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg); - if ((config_map & 3) != 3) { - continue; - } - if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8)) - ) == val) - { - return (config_map >> 16) & 0xff; - } - } - - return 0; -} - -u32 get_sblk(void) -{ - u32 reg; - /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); - return ((reg>>8) & 3); -} - - -u8 get_sbbusn(u8 sblk) -{ - return node_link_to_bus(0, sblk); -} diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c deleted file mode 100644 index fa4ab3cfd7..0000000000 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void setup_default_resource_map(void) -{ - static const u32 register_values[] = { - /* Careful set limit registers before base registers which contain - the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with - * interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit - * address that define the end of the DRAM region. - */ - ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, - ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001, - ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002, - ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003, - ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004, - ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005, - ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006, - ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit - * address that define the start of the DRAM region. - */ - ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000, - ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit - * address that defines the end of a memory-mapped - * I/O region n - */ - ADDRMAP_REG(0x84), 0x00000048, 0x00000000, - ADDRMAP_REG(0x8C), 0x00000048, 0x00000000, - ADDRMAP_REG(0x94), 0x00000048, 0x00000000, - ADDRMAP_REG(0x9C), 0x00000048, 0x00000000, - ADDRMAP_REG(0xA4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xAC), 0x00000048, 0x00000000, - ADDRMAP_REG(0xB4), 0x00000048, 0x00000000, - ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit - * address that defines the start of memory-mapped - * I/O region i - */ - ADDRMAP_REG(0x80), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x88), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x90), 0x000000f0, 0x00000000, - ADDRMAP_REG(0x98), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000, - ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000, - ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000, - ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in - * the range 3B0-3BB or 3C0-3DF independent of the - * base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of - * eack 1K block from matching agains this base/limit - * pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003, - ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000, - ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in - * configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in - * configuration regin i - */ - ADDRMAP_REG(0xE0), 0x0000FC88, 0xff000003, - ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000, - ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000, - }; - - u32 max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c deleted file mode 100644 index 735d72bbf7..0000000000 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <stdint.h> -#include <console/console.h> -#include <device/pci_ops.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdfam10/amdfam10.h> - -#define RES_DEBUG 0 - -void setup_resource_map(const u32 *register_values, u32 max) -{ - u32 i; - - for (i = 0; i < max; i += 3) { - pci_devfn_t dev; - u32 where; - u32 reg; - - dev = register_values[i] & ~0xfff; - where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } -} - - -void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) -{ - u32 i; - - for (i = 0; i < max; i += 3) { - pci_devfn_t dev; - u32 where; - unsigned long reg; - dev = (register_values[i] & ~0xfff) + offset_pci_dev; - where = register_values[i] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2] + offset_io_base; - pci_write_config32(dev, where, reg); - } -} - -void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) -{ - u32 i; - - if (RES_DEBUG) - printk(BIOS_DEBUG, "setting up resource map ex offset....\n"); - - for (i = 0; i < max; i += 4) { - if (RES_DEBUG) - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", - i/4, register_values[i], - register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), - register_values[i+2], - register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0) - ); - switch (register_values[i]) { - case RES_PCI_IO: //PCI - { - pci_devfn_t dev; - u32 where; - u32 reg; - dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; - where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); - if (RES_DEBUG) - printk(BIOS_SPEW, "WAS: %08x\n", reg); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - pci_write_config32(dev, where, reg); - if (RES_DEBUG) - printk(BIOS_SPEW, "NOW: %08x\n", reg); - } - break; - case RES_PORT_IO_8: // io 8 - { - u32 where; - u32 reg; - where = register_values[i+1] + offset_io_base; - reg = inb(where); - if (RES_DEBUG) - printk(BIOS_SPEW, "WAS: %08x\n", reg); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outb(reg, where); - if (RES_DEBUG) - printk(BIOS_SPEW, "NOW: %08x\n", reg); - } - break; - case RES_PORT_IO_32: //io32 - { - u32 where; - u32 reg; - where = register_values[i+1] + offset_io_base; - reg = inl(where); - if (RES_DEBUG) - printk(BIOS_SPEW, "WAS: %08x\n", reg); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outl(reg, where); - if (RES_DEBUG) - printk(BIOS_SPEW, "NOW: %08x\n", reg); - } - break; - } - } - - if (RES_DEBUG) - printk(BIOS_DEBUG, "done.\n"); -} - -void setup_resource_map_x(const u32 *register_values, u32 max) -{ - u32 i; - - if (RES_DEBUG) - printk(BIOS_DEBUG, "setting up resource map ex offset....\n"); - - for (i = 0; i < max; i += 4) { - if (RES_DEBUG) - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", - i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); - switch (register_values[i]) { - case RES_PCI_IO: //PCI - { - pci_devfn_t dev; - u32 where; - u32 reg; - dev = register_values[i+1] & ~0xfff; - where = register_values[i+1] & 0xfff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - pci_write_config32(dev, where, reg); - } - break; - case RES_PORT_IO_8: // io 8 - { - u32 where; - u32 reg; - where = register_values[i+1]; - reg = inb(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outb(reg, where); - } - break; - case RES_PORT_IO_32: //io32 - { - u32 where; - u32 reg; - where = register_values[i+1]; - reg = inl(where); - reg &= register_values[i+2]; - reg |= register_values[i+3]; - outl(reg, where); - } - break; - } - } - - if (RES_DEBUG) - printk(BIOS_DEBUG, "done.\n"); -} diff --git a/src/northbridge/amd/amdfam10/thermal_mixin.asl b/src/northbridge/amd/amdfam10/thermal_mixin.asl deleted file mode 100644 index fb33772c1e..0000000000 --- a/src/northbridge/amd/amdfam10/thermal_mixin.asl +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Include this file into a mainboard DSDT inside the PCI device - * "Northbridge Miscellaneous Control (Northbridge function 3)" and it - * will expose the temperature sensor of the processor as a thermal - * zone. - * - * Families 10 through 14 and some family 15 CPUs are supported. - * - * If, for example, the NB Misc. Control device is on 0:18.3, include - * the following: - * - * Scope (\_SB.PCI0) { - * Device (K10M) { - * Name (_ADR, 0x00180003) - * #include <northbridge/amd/amdfam10/thermal_mixin.asl> - * } - * } - * - * Do not include this if the board is affected by erratum 319 as the - * thermal sensor of Socket F/AM2+ processors may be unreliable. - * (Erratum 319 affects AM2+ boards, AM3 and later should be fine) - */ - -#ifndef K10TEMP_HOT_OFFSET -# define K10TEMP_HOT_OFFSET 100 -#endif - -#define K10TEMP_KELVIN_OFFSET 2732 -#define K10TEMP_TLIMIT_OFFSET 520 - -OperationRegion (TCFG, PCI_Config, 0x64, 0x4) -Field (TCFG, ByteAcc, NoLock, Preserve) { - HTCE, 1, /* Hardware thermal control enable */ - , 15, - TLMT, 7, /* (LimitTmp - 52) / 0.5 */ - , 9, -} - -OperationRegion (TCTL, PCI_Config, 0xa4, 0x4) -Field (TCTL, ByteAcc, NoLock, Preserve) { - , 21, - TNOW, 11, /* CurTmp / 0.125 */ -} - -ThermalZone (TZ00) { - Name (_HID, EisaId ("PNP0C11")) - Name (_STR, Unicode ("AMD CPU Core Thermal Sensor")) - - Method (_STA) { - If (LEqual (HTCE, One)) { - Return (0x0F) - } - Return (Zero) - } - - Method (_TMP) { /* Current temp in tenths degree Kelvin. */ - Multiply (TNOW, 10, Local0) - ShiftRight (Local0, 3, Local0) - Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) - } - - Method (_CRT) { /* Critical temp in tenths degree Kelvin. */ - Multiply (TLMT, 10, Local0) - ShiftRight (Local0, 1, Local0) - Add (Local0, K10TEMP_TLIMIT_OFFSET, Local0) - Return (Add (Local0, K10TEMP_KELVIN_OFFSET)) - } - - Method (_HOT) { /* Hot temp in tenths degree Kelvin. */ - Return (Subtract (_CRT, K10TEMP_HOT_OFFSET)) - } -} diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c deleted file mode 100644 index ed5556ff70..0000000000 --- a/src/northbridge/amd/amdfam10/util.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Vincent Legoll <vincent.legoll@gmail.com> - * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * fam10 northbridge utilities (dump routing registers). - * Designed to be called at any time. - * It can be called before RAM is set up by including this file. - * It can be called after RAM is set up by including amdfam10.h and enabling the - * compilation of this file in src/northbridge/amd/amdfam10/Makefile.inc. - */ -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ops.h> - -#include "amdfam10.h" - -/* Function 1 */ -/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at - * 0x78, 0xb8, and 0xd8 - */ -#define DRAM_ROUTE_START 0x40 -#define DRAM_ROUTE_END 0x78 -#define MMIO_ROUTE_START 0x80 -#define MMIO_ROUTE_END 0xb8 -#define PCIIO_ROUTE_START 0xc0 -#define PCIIO_ROUTE_END 0xd8 -#define CONF_ROUTE_START 0xe0 -#define CONF_ROUTE_END 0xec - -#define BITS(r, shift, mask) (((r>>shift)&mask)) - -/** - * Return "R" if the register has read-enable bit set. - */ -static const char *re(u32 i) -{ - return ((i & 1) ? "R" : ""); -} - -/** - * Return "W" if the register has write-enable bit set. - */ -static const char *we(u32 i) -{ - return ((i & 1) ? "W" : ""); -} - -/** - * Return a string containing the interleave settings. - */ -static const char *ileave(u32 base) -{ - switch ((base >> 8) & 7) { - case 0: - return "No interleave"; - case 1: - return "2 nodes"; - case 3: - return "4 nodes"; - case 7: - return "8 nodes"; - default: - return "Reserved"; - } -} - -/** - * Return the node number. - * For one case (config registers) these are not the right bit fields. - */ -static int r_node(u32 reg) -{ - return BITS(reg, 0, 0x7); -} - -/** - * Return the link number. - * For one case (config registers) these are not the right bit fields. - */ -static int r_link(u32 reg) -{ - return BITS(reg, 4, 0x3); -} - -/** - * Print the DRAM routing info for one base/limit pair. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and interleave information. - * - * @param level Printing level - * @param which Register number - * @param base Base register - * @param lim Limit register - */ -static void showdram(int level, u8 which, u32 base, u32 lim) -{ - printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", - which, (((u64) base & 0xffff0000) << 8), - (((u64) lim & 0xffff0000) << 8) + 0xffffff, - r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); -} - -/** - * Print the config routing info for a config register. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and device number compare enable - * - * @param level Printing level - * @param which Register number - * @param reg Config register - */ -static void showconfig(int level, u8 which, u32 reg) -{ - /* Don't use r_node() and r_link() here. */ - printk(level, "Config(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", - which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), - BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), - re(reg), we(reg), - BITS(reg, 2, 0x1)?"dev":"bus"); -} - -/** - * Print the PCIIO routing info for one base/limit pair. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and VGA and ISA Enable. - * - * @param level Printing level - * @param which Register number - * @param base Base register - * @param lim Limit register - */ -static void showpciio(int level, u8 which, u32 base, u32 lim) -{ - printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", - which, BITS(base, 12, 0x3fff) << 12, - (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), - re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); -} - -/** - * Print the MMIO routing info for one base/limit pair. - * - * Show base, limit, dest node, dest link on that node, read and write - * enable, and CPU Disable, Lock, and Non-posted. - * - * @param level Printing level - * @param which Register number - * @param base Base register - * @param lim Limit register - */ -static void showmmio(int level, u8 which, u32 base, u32 lim) -{ - printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " - "CPU disable %d, Lock %d, Non posted %d\n", - which, ((u64) BITS(base, 0, 0xffffff00)) << 8, - (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), - r_link(lim), re(base), we(base), BITS(base, 4, 0x1), - BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); -} - -/** - * Show all DRAM routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showalldram(int level, struct device *dev) -{ - u8 reg; - for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) { - u32 base = pci_read_config32(dev, reg); - u32 lim = pci_read_config32(dev, reg + 4); - if (base || lim!=(reg-DRAM_ROUTE_START)/8) - showdram(level, reg, base, lim); - } -} - -/** - * Show all MMIO routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showallmmio(int level, struct device *dev) -{ - u8 reg; - for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) { - u32 base = pci_read_config32(dev, reg); - u32 lim = pci_read_config32(dev, reg + 4); - if (base || lim) - showmmio(level, reg, base, lim); - } -} - -/** - * Show all PCIIO routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showallpciio(int level, struct device *dev) -{ - u8 reg; - for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) { - u32 base = pci_read_config32(dev, reg); - u32 lim = pci_read_config32(dev, reg + 4); - if (base || lim) - showpciio(level, reg, base, lim); - } -} - -/** - * Show all config routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -static void showallconfig(int level, struct device *dev) -{ - u8 reg; - for (reg = CONF_ROUTE_START; reg <= CONF_ROUTE_END; reg += 4) { - u32 val = pci_read_config32(dev, reg); - if (val) - showconfig(level, reg, val); - } -} - -/** - * Show all routing registers. This function is callable at any time. - * - * @param level The debug level. - * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. - */ -void showallroutes(int level, struct device *dev) -{ - showalldram(level, dev); - showallmmio(level, dev); - showallpciio(level, dev); - showallconfig(level, dev); -} |