diff options
Diffstat (limited to 'src/northbridge/amd/amdfam10/conf.c')
| -rw-r--r-- | src/northbridge/amd/amdfam10/conf.c | 298 |
1 files changed, 0 insertions, 298 deletions
diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c index 6688e0addb..9db685bef9 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/conf.c @@ -53,246 +53,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -#if !CONFIG_AMDMCT -static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) -{ - u32 i; - device_t dev; - u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi; - u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg; - d_mask_lo = (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones - d_mask_hi = (d.mask>>21) & 0xff; - d_base_lo = ((d.base<<(8+3)) & 0xffff0000); - if (d.mask & 1) d_base_lo |= 3; - d_base_hi = (d.base>>21) & 0xff; - d_mask_lo_reg = 0x44+(nodeid<<3); - d_mask_hi_reg = 0x144+(nodeid<<3); - d_base_lo_reg = 0x40+(nodeid<<3); - d_base_hi_reg = 0x140+(nodeid<<3); - - for (i=0;i<nodes;i++) { -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); -#else - dev = __f1_dev[i]; -#endif - pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones - pci_write_config32(dev, d_mask_hi_reg, d_mask_hi); - pci_write_config32(dev, d_base_lo_reg, d_base_lo); - pci_write_config32(dev, d_base_hi_reg, d_base_hi); - } - -#if defined(__PRE_RAM__) - dev = NODE_PCI(nodeid, 1); -#else - dev = __f1_dev[nodeid]; -#endif - pci_write_config32(dev, 0x120, d.base>>8); - pci_write_config32(dev, 0x124, d.mask>>8); - -} -#endif - -#if !CONFIG_AMDMCT -static void set_DctSelBaseAddr(u32 i, u32 sel_m) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= ~(DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT); - dcs_lo |= (sel_m<<(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27)); - pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo); - -} - - -static u32 get_DctSelBaseAddr(u32 i) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 sel_m; - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= DCSL_DctSelBaseAddr_47_27_MASK<<DCSL_DctSelBaseAddr_47_27_SHIFT; - sel_m = dcs_lo>>(20+DCSL_DctSelBaseAddr_47_27_SHIFT-27); - return sel_m; -} - -#ifdef UNUSED_CODE -static void set_DctSelHiEn(u32 i, u32 val) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= ~(7); - dcs_lo |= (val & 7); - pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo); - -} -#endif - -static u32 get_DctSelHiEn(u32 i) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_lo; - dcs_lo = pci_read_config32(dev, DRAM_CTRL_SEL_LOW); - dcs_lo &= 7; - return dcs_lo; - -} - -static void set_DctSelBaseOffset(u32 i, u32 sel_off_m) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 dcs_hi; - dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH); - dcs_hi &= ~(DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT); - dcs_hi |= sel_off_m<<(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26); - pci_write_config32(dev, DRAM_CTRL_SEL_HIGH, dcs_hi); - -} - -#ifdef UNUSED_CODE -static u32 get_DctSelBaseOffset(u32 i) -{ - device_t dev; -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 2); -#else - dev = __f2_dev[i]; -#endif - u32 sel_off_m; - u32 dcs_hi; - dcs_hi = pci_read_config32(dev, DRAM_CTRL_SEL_HIGH); - dcs_hi &= DCSH_DctSelBaseOffset_47_26_MASK<<DCSH_DctSelBaseOffset_47_26_SHIFT; - sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26); - return sel_off_m; -} -#endif - -static u32 get_one_DCT(struct mem_info *meminfo) -{ - u32 one_DCT = 1; - if (meminfo->is_Width128) { - one_DCT = 1; - } else { - u32 dimm_mask = meminfo->dimm_mask; - if ((dimm_mask >> DIMM_SOCKETS) && (dimm_mask & ((1<<DIMM_SOCKETS)-1))) { - one_DCT = 0; - } - } - - return one_DCT; -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -// See that other copy in northbridge.c -static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) -{ - u32 ii; - u32 carry_over; - device_t dev; - struct dram_base_mask_t d; - u32 sel_m; - u32 sel_hi_en; - u32 hoist; - - - carry_over = (4*1024*1024) - hole_startk; - - for (ii=nodes - 1;ii>i;ii--) { - d = get_dram_base_mask(ii); - if (!(d.mask & 1)) continue; - d.base += (carry_over>>9); - d.mask += (carry_over>>9); - set_dram_base_mask(ii, d, nodes); - - if (get_DctSelHiEn(ii) & 1) { - sel_m = get_DctSelBaseAddr(ii); - sel_m += carry_over>>10; - set_DctSelBaseAddr(ii, sel_m); - } - - } - d = get_dram_base_mask(i); - d.mask += (carry_over>>9); - set_dram_base_mask(i,d, nodes); -#if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); -#else - dev = __f1_dev[i]; -#endif - sel_hi_en = get_DctSelHiEn(i); - if (sel_hi_en & 1) { - sel_m = get_DctSelBaseAddr(i); - } - if (d.base == (hole_startk>>9)) { - //don't need set memhole here, because hole off set will be 0, overflow - //so need to change base reg instead, new basek will be 4*1024*1024 - d.base = (4*1024*1024)>>9; - set_dram_base_mask(i, d, nodes); - - if (sel_hi_en & 1) { - sel_m += carry_over>>10; - set_DctSelBaseAddr(i, sel_m); - } - } else { - hoist = /* hole start address */ - ((hole_startk << 10) & 0xff000000) + - /* enable */ - 1; - if (one_DCT||(sel_m>=(hole_startk>>10))) { //one DCT or hole in DCT0 - hoist += - /* hole address to memory controller address */ - ((((d.base<<9) + carry_over) >> 6) & 0x0000ff00) ; - - if (sel_hi_en & 1) { - sel_m += (carry_over>>10); - set_DctSelBaseAddr(i, sel_m); - set_DctSelBaseOffset(i, sel_m); - } - } else { // hole in DCT1 range - hoist += - /* hole address to memory controller address */ - ((((sel_m<<10) + carry_over) >> 6) & 0x0000ff00) ; - // don't need to update DctSelBaseAddr - if (sel_hi_en & 1) { - set_DctSelBaseOffset(i, sel_m); - } - } - pci_write_config32(dev, 0xf0, hoist); - - } - - return carry_over; -} -#endif -#endif // CONFIG_AMDMCT - static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 busn_min, u32 busn_max, u32 segbit, @@ -402,43 +162,6 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } #endif -#ifdef UNUSED_CODE -static void re_set_all_config_map_reg(u32 nodes, u32 segbit, - sys_info_conf_t *sysinfo) -{ - u32 ht_c_index; - device_t dev; - - set_config_map_reg(0, sysinfo->sblk, 0, 0, sysinfo->ht_c_conf_bus[0]>>20, segbit, nodes); - - /* clean others */ - for (ht_c_index=1;ht_c_index<4; ht_c_index++) { - u32 i; - for (i=0; i<nodes; i++) { - #if defined(__PRE_RAM__) - dev = NODE_PCI(i, 1); - #else - dev = __f1_dev[i]; - #endif - pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); - } - } - - for (ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) { - u32 nodeid, linkn; - u32 busn_max; - u32 busn_min; - nodeid = (sysinfo->ht_c_conf_bus[ht_c_index] >> 2) & 0x3f; - linkn = (sysinfo->ht_c_conf_bus[ht_c_index]>>8) & 0x7; - busn_max = sysinfo->ht_c_conf_bus[ht_c_index]>>20; - busn_min = (sysinfo->ht_c_conf_bus[ht_c_index]>>12) & 0xff; - busn_min |= busn_max & 0xf00; - set_config_map_reg(nodeid, linkn, ht_c_index, busn_min, busn_max, segbit, nodes); - } - -} -#endif - static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) { u32 tempreg; @@ -480,27 +203,6 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, } -#ifdef UNUSED_CODE -static void set_BusSegmentEn(u32 node, u32 segbit) -{ -#if CONFIG_PCI_BUS_SEGN_BITS - u32 dword; - device_t dev; - -#if defined(__PRE_RAM__) - dev = NODE_PCI(node, 0); -#else - dev = __f0_dev[node]; -#endif - - dword = pci_read_config32(dev, 0x68); - dword &= ~(7<<28); - dword |= (segbit<<28); /* bus segment enable */ - pci_write_config32(dev, 0x68, dword); -#endif -} -#endif - #if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) { |