diff options
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn/northbridge.c')
-rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7b57cc31e5..0bd6cfb9ff 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -79,9 +79,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -93,7 +93,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg |= PCI_IO_BASE_NO_ISA; } #endif - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -103,10 +103,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) + for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<node_nums; i++) + for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -409,9 +409,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) #endif break; } @@ -629,7 +628,7 @@ static void domain_read_resources(device_t dev) if ((base & 3) != 0) { unsigned nodeid, reg_link; device_t reg_dev; - if (reg<0xc0) { // mmio + if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); @@ -696,7 +695,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i=0; i<node_nums; i++) { + for (i = 0; i < node_nums; i++) { dram_base_mask_t d; resource_t base_k, limit_k; d = get_dram_base_mask(i); @@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev) //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if (pre_sizek>0) { + if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -971,7 +970,7 @@ static void cpu_bus_scan(device_t dev) } sysconf_init(dev_mc); #if CONFIG_CBB && (MAX_NODE_NUMS > 32) - if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe if (pci_domain->link_list && !pci_domain->link_list->next) { struct bus *new_link = new_link(pci_domain); pci_domain->link_list->next = new_link; @@ -1052,7 +1051,7 @@ static void cpu_bus_scan(device_t dev) printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - for (j = 0; j <= siblings; j++ ) { + for (j = 0; j <= siblings; j++) { extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; |