diff options
Diffstat (limited to 'src/northbridge/amd/agesa/family14')
-rw-r--r-- | src/northbridge/amd/agesa/family14/Makefile.inc | 5 | ||||
-rw-r--r-- | src/northbridge/amd/agesa/family14/northbridge.c | 9 | ||||
-rw-r--r-- | src/northbridge/amd/agesa/family14/state_machine.c | 94 |
3 files changed, 105 insertions, 3 deletions
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index 6b2ca784cd..41c40c3915 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -16,3 +16,8 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y) +romstage-y += state_machine.c +ramstage-y += state_machine.c +endif diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index d5bf73091d..34e7ce6934 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -32,6 +32,7 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <sb_cimx.h> @@ -581,6 +582,10 @@ static void domain_set_resources(device_t dev) static void domain_enable_resources(device_t dev) { +#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); + #if IS_ENABLED(CONFIG_AMD_SB_CIMX) if (!acpi_is_wakeup_s3()) { sb_After_Pci_Init(); @@ -590,9 +595,6 @@ static void domain_enable_resources(device_t dev) } #endif - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio(); @@ -601,6 +603,7 @@ static void domain_enable_resources(device_t dev) } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +#endif } static const char *domain_acpi_name(struct device *dev) diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c new file mode 100644 index 0000000000..fbc2d7e1e5 --- /dev/null +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(&Resume->S3DataBlock); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + amd_initenv(); +#if 0 + /* FIXME: It's only in ramstage. */ + sb_Before_Pci_Init(); +#endif +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(&S3Late->S3DataBlock); +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +#if 0 + /* FIXME: It's only in ramstage. */ + sb_Before_Pci_Restore_Init(); +#endif +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(&S3Save->S3DataBlock); +} |